AR6102 ROCmTM MAC/BB/Radio for 2.4 GHz Embedded WLAN Applications
General Description
The Atheros AR6102 is a member of the WLAN ROCm family of chips. The compact size and low power consumption of this design make it an ideal vehicle for adding WLAN to hand-held and other battery-powered consumer electronic devices. The IEEE 802.11g (2.4 GHz) standard is supported by this chipset.
The AR6102 family includes a highly
integrated, RF front-end (Power Amplifier, Low-Noise Amplifier and RF switch) and high-frequency reference clock, enabling low-cost designs with minimal external components. Advanced architecture and protocol techniques save power during sleep, stand-by and active states.
The AR6102 family supports 2, 3 and 4 wire Bluetooth coexistence protocols with advanced algorithms for predicting channel usage by the co-located Bluetooth transceiver. A 26MHz reference clock output is also available,
eliminating the need for a dedicated BT clock.The AR6102 provides multiple peripheral interfaces including UART.
AR6102 Features
■IEEE 802.11b/g compliant
■Data rates of 1–Mbps for 802.11g
■Advanced power management to minimize
standby, sleep and active power
■Security support for WPS, WPA2, WPA,
WAPI and protected management frames■Support for 2.4 GHz operation in all
available bands in all regulatory domains
■Full 802.11e QoS support including WMM
and U-APSD
■Support for fast Tx and Rx antenna
AorehtC sfnoneiddiversity allowing optimal antenna
selection on a per-packet basisinterfaces.
■Supports both SDIO 1.1 and GSPI host ■Standard 2, 3 and 4 wire Bluetooth
laticoexistence handshake support
■16550-compliant UART
■Wake-on-Wireless (WoW) maximizes host
sleep duration
■7.4 x 8 mm LGA package
■Pre-certified to meet FCC, ETSI, and TELEC
standards
■Integrated PA, LNA, RF switch and High
Freq Reference Clock, minimizing external
component count
■Integrated RF shielding
■Suports cellular co-existence with an
external band-pass filter
Atheros AR6102 Block Diagram
© 2009 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Atheros XR®, Driving the Wireless Future®, ROCm®, Super A/G®, Super G®, Total 802.11®, and Wake on Wireless® are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain Technology™, the Air is Cleaner at 5-GHz™, XSPAN®, Wireless Future. Unleashed Now.®, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice
ATHEROS CONFIDENTIAL•1
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Table of Contents
1Dimensions and Footprint..........52Pin Assignment and Description9
2.1Pin Description.......................................11
5.9.2Dedicated Function Pins...........325.10RF Port Matching...............................335.11External 32KHz Sleep Clock.............335.12Clock Sharing......................................335.13Host Configuration Guidelines........335.14Layout Guidelines..............................34
5.14.1General Guidelines.................345.14.2Component Placement..............345.15VDD_12 and VDD_1.2VA
Power Trace Routing.........................345.15.3Host Interface Layout................355.15.432KHz Clock Signal Layout......355.15.5Grounding...................................36
3Electrical Characteristics............15
3.1Absolute Maximum Ratings................153.23.33.43.53.6
Recommended Operating
Conditions...........................................15DC Electrical Characteristics............16Radio Receiver Characteristics.........17Radio Transmitter Characteristics...18Synthesizer Composite Characteristics for 2.4GHz
Operation.............................................18Typical Power Consumption............193.7.1Measurement Conditions for Low
Power State...............................19
3.7.2Measurement Conditions for
Continuous Receive....................203.7.3Measurement Conditions for
Continuous Transmit.................20Power Sequence Operation...............21
3.7
6Assembly Guidelines..................37
6.1
3.8
4AC Specifications........................23
4.1External 32KHz Input Clock Timing..234.2
SDIO/GSPI Interface Timing...........24
Aehtsrono Cdif7
6.2
enReflow profile.....................................37
Solder material recommendations...37
latiPackage Marking Information..39
8Ordering Information.................41
5Application Guidelines.............25
5.1Typical 11b/g Application...................255.25.35.45.55.65.75.85.9
Application Schematic.......................2511b/g Application with Cellular
Coexistence Filter...............................2611b/g Application with Bluetooth-Coexistence..........................................2711b/g Application with Antenna
Diversity..............................................30Power Supply Management.............30Supply Ripple Tolerance...................30Grounding...........................................32Host Interfaces and GPIOs................325.9.1Secure Digital Input/Output
(SDIO)........................................32
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1.Dimensions and Footprint
This section provides the dimensions and footprint of the AR6102. Figure1-1 shows the top and side view of the AR6102.
htAorefnoCs neidlatiFigure1-1. Dimensions and Footprint - Top and Side View
Figure1-2 shows the bottom view of the
AR6102.
Atheros Communications, Inc.ATHEROS CONFIDENTIALAR6102 ROCm® Data Sheet•
June 2009•55AorehtC sfnoneidlatiFigure1-2. Dimensions and Footprint - Bottom View
6
6•AR6102 ROCm® Data SheetJune 2009Atheros Communications, Inc.
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htAorefnoCs neidlatiFigure1-3. Dimensions and Footprint - Bottom View Details
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2.Pin Assignment and Description
This section provides pin assignments descriptions.
The following nomenclature is used for signal types described in this chapter.
The following nomenclature is used for signal names:NC_LA_I/OI PU
No connection should be made to this pin
At the end of the signal name, indicates active low signalsAnalog input signalDigital input signal
Weak internal pull-up, to prevent signals from floating when left open
Weak internal pull-down, to prevent signals from floating when left open
A digital bidirectional signalA digital output signal
PD
I/OOP
A power or ground signal
See Table2-1 for the AR6102 package pin assignments.
htAorefnoCs neidlatiAtheros Communications, Inc.
ATHEROS CONFIDENTIALAR6102 ROCm® Data Sheet•
June 200999Table2-1. Pin Assignment
Pin No.
A1A2A3A4A5A6A7A8A9B2B3B4B5B6B7B8B9C2C3C4C5C6C7C8C9D2D3D4D5D6D7D8D9E3E4E5E6E7E8E9F3F4F5F6Name
GNDVCC_FEMBT_CLK_OUTVDD_12JTAG_SELCLK_REQSYS_RST_LSD_D0SD_CLKVCC_FEMBT_CLK_ENRSVD_BBPITXD0
CHIP_PWD_LSD_D1SD_D2TDIGNDVDD_1.2VAGNDGNDWAKE_ON_WLANSD_D3TDOTMSGNDGNDGNDGNDGNDSD_CMDTCKCLK32KGNDGNDGNDGNDDVDD_SDIOHMODE_1BT_PRIORITYGNDGNDGNDVCC_FEMPin No.
F7F8F9G4G5G6G7G8G9H1H4H5H6H7H8H9GND-1GND-2GND-3GND-4GND-5GND-6GND-7GND-8GND-9GND-10GND-11GND-12GND-13GND-14GND-15GND-16GND-17GND-18Name
VDD_BTWLAN_ACTIVEVDD18VDD_GPIOXTALOANTDANTEGNDVDD18RF_OUTGNDANTABT_FREQBT_ACTIVEGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDAorehtC sfnoneidlati10
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2.1Pin Description
Table2-2 describes the pins.
Table2-2. Pin Description
Pin No.
B2A2F6C3A4F7G4E7F9G9A1C2C4C5D2D3D4D5D6E3E4E5E6F3F4F5G8H4H8H9GND-1GND-2
Name
VCC_FEM
P
TypeDescription
Power Supply
Supply for front-end components and switch control lines.Analog 1.2V supplyDigital 1.2V supplyBT-coexistence I/O SupplyGPIO supply voltageHost interface supply voltage
Analog 1.8V supplyAnalog 1.8V supplyGround connections
Reset State
N/A
Pad Power Supply Domain
N/A
VDD_1.2VAVDD_12VDD_BTVDD_GPIODVDD_SDIOVDD18VDD18GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
PPPPPPPPPPPP
N/AN/AN/AN/AN/A
N/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/A
htAPPPPPPPPPPPPPPPPP
orefnoCs Ground connections
Ground connections
edintlaiN/A
N/A
N/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/A
Ground connections
Ground connections
Ground connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connections
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ATHEROS CONFIDENTIALAR6102 ROCm® Data Sheet•11
June 200911Table2-2. Pin Description (continued)
Pin No.
GND-2GND-3GND-4GND-5GND-6GND-7GND-8GND-9GND-10GND-11GND-12GND-13GND-14GND-15GND-16GND-17GND-18A8B7B8C7D7A9H1E9
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDSD_D0SD_D1SD_D2SD_D3DS_CMDSD_CLKRF_OUTBT_PRIORITY
Name
PPPPPPPPPPPPPPPPP
TypeDescription
Ground connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connectionsGround connectionsHost Interface
Reset State
N/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/APUPUPUPUPU---
Pad Power Supply Domain
N/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/AN/ADVDD_SDIODVDD_SDIODVDD_SDIODVDD_SDIODVDD_SDIODVDD_SDIO-VDD_BT
AehtI/OI/OI/OII
I/O
srooC nfedilaitnSDIO data signal
SDIO data signalSDIO data signalSDIO data signalSDIO command signalSDIO clock signal
RF PortRF I/O port
Input to WLAN indicating
BT Status. Leave as NC when unused.
A_I/OI/0
Bluetooth Coexistence Interface
F8WLAN_ACTIVEI/0
Output to BT indicating PDWLAN Status. Leave as NC when unused.
Input to WLAN indicating BT Status. Leave as NC when unused.
Input to WLAN indicating BT Status
-
VDD_BT
H6BT_FREQI/0VDD_BT
H7BT_ACTIVEI/0-VDD_BT
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Table2-2. Pin Description (continued)
Pin No.
H5G6G7D9G5
Name
ANTAANTDANTECLK32KXTALO
OOO
TypeDescription
Radio Control Signals
Control signal for external RF front-end components. Leave as NC when unused.Clocking Interface
Reset State
PDPUPD
Pad Power Supply Domain
VCC_FEM
II
Input for external 32KHz sleep clock.
Input for external reference clock oscillator. Leave as NC.
Buffered reference clock output. Leave as NC when unused.Digital ControlChip power down inputChip reset inputHost interface selection input
--
VDD_GPIO-
A3BT_CLK_OUTO--
B6A7E8A6B3
CHIP_PWD_LSYS_RST_LHMODE_1CLK_REQBT_CLK_EN
IIIOI
C6
WAKE_ON_WLANRSVD_BBPITXD0JTAG_SELTDITDOTCKTMS
B4B5A5B9C8D8C9
htAONCNCNCNCNCNCNC
orenoC sExternal oscillator enable
signal. Leave as NC.
difenlatiPD-PUPD
DVDD_SDIODVDD_SDIOVDD_GPIODVDD_SDIOVDD18
Input signal to enable -buffered clock output. Tie to
GND when unused.
PD
Output signal to interrupt host
System Test
Reserved for internal use. Leave as NC.
VDD_GPIO
---
--VDD_GPIODVDD_SDIO
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3.Electrical Characteristics
This section describes electrical characteristics of the AR6102.
3.1Absolute Maximum Ratings
See Table3-1
Table3-1. Absolute Maximum Ratings
Parameter
VDD_1.2VAVDD_12VDD_BTVDD_GPIODVDD_SDIOVDD18VCC_FEM
Min.
-0.3-0.3-0.3-0.3-0.3-0.3-0.3
Max.
1.351.3.04.04.02..2
Unit
VVVVV
3.2Recommended Operating Conditions
See Table3-2.
Table3-2. Recommneded Operating Conditions
Parameter
VCC_FEMVDD_1.2VAVDD_12VDD_BTVDD_GPIODVDD_SDIOVDD18
TcaseCommercial
Tcase Industrial[1]
htA3.01.141.141.711.711.711.71-20
Min.
orefnoCs Typ.
3.31.21.21.81.81.81.82525
neid3.61.261.263.463.463.461.8585
latiVV
Max.Unit
VVVVVVV°C°C
-40
[1]Contact Atheros Sales for Industrial grade parts
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ATHEROS CONFIDENTIALAR6102 ROCm® Data Sheet•15
June 2009153.3DC Electrical Characteristics
General DC Electrical Characteristics (For 3.3V I/O Operation)
Table3-3. General DC Electrical Characteristics (For 3.3V I/O Operation)
Symbol
VIHVILIIL
Parameter
High Level Input VoltageLow Level Input VoltageInput Leakage Current
ConditionsMin
0.8xVdd–0.3–10–65
Typ
--
Max
Vdd+0.30.2xVdd1065--0.400.40-Unit
VVμAμAVVVVpFWithout Pull-up 0V High Level Output VoltageIOH=–4mAIOH=–12mA[1]IOL=4mAIOL=12mA[1]-Vdd–0.35-Vdd–0.35------6Low Level Output VoltageInput Capacitance[2] [1]For these pins only: SDIO_DATA_0, SDIO_DATA_1, SDIO_DATA_2, SDIO_DATA_3 [2]Parameter not tested; value determined by design simulation Table3-4. General DC Electrical Characteristics (For 1.8V I/O Operation) Symbol VIHVILIIL Parameter High Level Input VoltageLow Level Input VoltageInput Leakage Current AWithout Pull-up 0V fnoneidlatiMin 0.8xVdd–0.3–10–35Typ ----Max Vdd+0.20.2xVdd1035--0.30.3-Unit VVμAμAVVVVpFWith Pull-up or 0V High Level Output VoltageVdd–0.35-Vdd–0.35------6Low Level Output VoltageInput Capacitance[2][1]For these pins only: SDIO_DATA_0, SDIO_DATA_1, SDIO_DATA_2, SDIO_DATA_3 [2]Parameter not tested; value determined by design simulation 1616•AR6102 ROCm® Data SheetJune 2009Atheros Communications, Inc. ATHEROS CONFIDENTIAL 3.4Radio Receiver Characteristics Table3-5 summarize the AR6102 receiver characteristics. Table3-5. Receiver Characteristics for 2.4 GHz Operation Symbol FrxSrf Parameter Receive input frequency rangeSensitivity1 Mbps2 Mbps5.5 Mbps11 Mbps6 Mbps9 Mbps12 Mbps18 Mbps24 Mbps36 Mbps48 Mbps Mbps Conditions 5 MHz channelspacing- Min 2.412 Typ - Max 2.484 Unit GHzdBm IP1dBIIP3ERphaseERampRadj Input 1 dB compression (min. gain)I,Q phase errorI,Q amplitude error - Input third intercept point (min.gain)- Adjacent channel rejection1 Mbps11 Mbps6 Mbps Mbps htAoreoCs - nfneidlati-8-2-4-1 -96 -92--85-91---87-83-80-75-73-98-93-92-88-93-92-91-88-85-82-77-75-2+30.50 -100-96-94-91-96-95-93-92-88-85-81-77--41 dBmdBmdegreedBdB 10 to 20MHz 34313522-363437241.5 ----- TRpowupTime for power up (from RxOn)μs Atheros Communications, Inc.ATHEROS CONFIDENTIALAR6102 ROCm® Data Sheet•17 June 2009173.5Radio Transmitter Characteristics Table3-6 a summarize the transmitter characteristics for AR6102. Table3-6. Transmitter Characteristics for 2.4 GHz Operation Symbol FtxPoutSPgain Parameter Transmit output frequency rangeMask Compliant CCK output power EVM Compliant OFDM output power for QAMPA gain step Conditions 5 MHz center frequency Min 2.412-- Typ -1515 Max 2.484-- Unit GHzdBmdBm See Note[1]- -1.5-2- 0.5- 1.5dB-2[2]2 dBdBμs AplTTpowup Accuracy of power leveling loop Time for power up (from -TxOn) [1]Guaranteed by design.[2]Overall temperature -20 to 85ºC 3.6Synthesizer Composite Characteristics for 2.4GHz Operation Table3-7. Synthesizer Composite Characteristics for 2.4 GHz Operation Symbol Pn Parameter Phase noise (at Tx_Out)At 30 KHz offsetAt 100 KHz offsetAt 500 KHz offsetAt 1 MHz offset Center channel frequencyReference oscillator frequencyPhase noise at BT_CLK_OUTAt 10KHz offsetAt 100KHz offsetAt 1MHz offset AorehtC sfnoneidlati1.5 Conditions -------- MinTyp –99 –99–108–115-26 Max -95-95-100-1052.484- Unit dBc/Hz Fc BT_CLK_OUTBT_CLK_OUT_Pn Center frequency at 2.3125 MHz spacing [1]± 20ppm - GHzMHz -149.3-160.1-1.1 1.2 --0.2 - dBc/Hz BT_CLK_OUT_AMP BT_CLK_OUT amplitudeTSpowup Time for power up (from sleep) V pk-pkms [1]Frequency is measured at the Tx output. 1818•AR6102 ROCm® Data SheetJune 2009Atheros Communications, Inc. ATHEROS CONFIDENTIAL 3.7Typical Power Consumption Table3-8 illustrate TYPICAL, room temperature power consumption data. Table3-8. AR6102 Typical Power Consumption - Low Power States Current Consumption [mA] Mode Standby CHIP_PWD Power Consumption [mW] 0.0100.0760.6193.511.580.91 @1.2 V 0.008 @1.8 V 0.0000.0070.0070.7070.2400.077 @3.3 V 0.0000.0010.0020.0420.0150.006 HOST_OFF 0.050SLEEP 0.500IEEE PS DTIM=1DTIM=3DTIM=10 1.7500.9170.625 3.7.1Measurement Conditions for Low Power State T_amb = 25 ºC All I/O pins except CHIP_PWD_L are maintained at their default polarities.VDD_1.2V = VDD_12 = 1.2 VVDD_BT = VDD_GPIO = VDD18_DVDD_SDIO = 1.8 VVCC_FEM = 3.3 V CHIP_PWD - all blocks power gated except for \"Power, Clock Management\" HOST_OFF - all blocks power gated except for \"Power, Clock Management\\"GSPI.\" SLEEP - \"LF CLK\" running; all blocks voltage scaled or power gated except for \"Power, Clock Management\internal state is maintained. Table3-9. AR6102 Typical Power Consumption - Rx Rx Power Consumption [mW] 134134140140138139139140141143 htA28282828282828282828 orefnoCs neidlatiCurrent Consumption [mA] Rate [Mbps] 125.5116912182436 @1.2 V 6969676868697071 @1.8 V@3.3 V 2222222222 Atheros Communications, Inc. ATHEROS CONFIDENTIALAR6102 ROCm® Data Sheet•19 June 200919Table3-9. AR6102 Typical Power Consumption - Rx Rx Current Consumption [mA] 48 7373 2828 22 Power Consumption 145145 3.7.2Measurement Conditions for Continuous Receive T_amb = 25 ºC VDD_12 = VDD_1.2VA = 1.2 V VDD18 = 1.8 V = DVDD_SDIO = VDD_GPIO = VDD_BTVCC_FEM = 3.3V CHIP_PWD - all blocks power gated except for \"Power, Clock Management\" HOST_OFF - all blocks power gated except for \"Power, Clock Management\\"GSPI.\" SLEEP - \"LF CLK\" running; all blocks voltage scaled or power gated except for \"Power, Clock Management\internal state is maintained. Table3-10. AR6102 Typical Power Consumption - Tx Current Consumption [mA] Rate [Mbps] 125.5116912182438 Target Output Power [dBm]@1.2 V 151515151515151515141312 3737 Aeht37374444444445 srono C@1.8 V 515151516565656565585565 dif@3.3 V enlatiTotal Power Consumption [mW] 5525525525525795795795795801513518 126126126126124124124124124116109105 3.7.3Measurement Conditions for Continuous Transmit T_amb = 25 ºC VDD_12 = VDD_1.2VA = 1.2 V VDD18 = 1.8 V = DVDD_SDIO = VDD_GPIO = VDD_BTVCC_FEM = 3.3V 2020•AR6102 ROCm® Data SheetJune 2009Atheros Communications, Inc. ATHEROS CONFIDENTIAL 3.8Power Sequence Operation I/O Supply = VDD18, DVDD_SDIO, VDD_GPIO, VDD_BT, VCC_FEM1.2V Supply = VDD_1.2VA, VDD_12 NOTE:It is important that all I/O supplies come up at the same time. CHIP_PWD_L or SYS_RST_L need to be toggled after all supplies are stable in order to ensure proper reset. I/O Supply1.2V SupplyCHIP_PWD_LSYS_RST_LTaTbTcTdFigure3-1. Power Up/Power Down Timing While Asserting CHIP_PWD_L I/O Supply1.2V SupplyCHIP_PWD_LSYS_RST_LTahtATeoreTffnoCs neidlatiTcTdFigure3-2. Power Up/Down Timing While Asserting SYS_RST_L I/O Supply1.2V SupplyCHIP_PWD_LSYS_RST_LTfTgFigure3-3. Reset and Power Cycle Timing Atheros Communications, Inc. ATHEROS CONFIDENTIALAR6102 ROCm® Data Sheet•21 June 2009•21Table3-11. Timing Diagram Definitions Description TaTbTcTdTeTfTg Time between I/O supply valid** and 1.2V supply valid Time between 1.2V supply valid and CHIP_PWD_L deassertion Time between CHIP_PWD_L or SYS_RST_L assertion and 1.2V supply invalid Time between CHIP_PWD_L or SYS_RST_L assertion and 1.2V supply invalidTime between 1.2V supply valid and SYS_RST_L assertionLength of SYS_RST_L pulseLength of CHIP_PWD_L pulse Min (μsec) 0[1]50N/A***015 [1]If Ta were negative, there would be additional leakage power which would not exceed 15mW on the 1.2V supply and 150uW on the I/O supply under recommended operating conditions. There would be no functional impact as long as the remainder of the power up timing is followed. ** Supply valid represents the voltage level has reached 90% level.*** No strict requirement for this parameter. This parameter can also be negative. AorehtC sfnoneidlati22 22•AR6102 ROCm® Data SheetJune 2009Atheros Communications, Inc. ATHEROS CONFIDENTIAL 4.AC Specifications 4.1External 32KHz Input Clock Timing Figure4-1 and Table4-1 show the external 32KHz input clock timing requirements. 1/ CK1 CK6 CK7 CK2 CK3Figure4-1. External 32 KHz Input Clock Timing Requirements Table4-1. External 32 KHz Input Clock Timing Symbol CK1CK2CK3CK4CK5CK6CK7 Description FrequencyFall timeRise time Min - Duty cycle (high-to-low ratio)Frequency stabilityInput high voltageInput low voltage htAorefnoCs 1115–50-0.3 neid------ Typ 32.768 lati- Max 1001008550 VDD_BT+0.20.2*VDD_BT Unit KHznsns%ppmVV 0.8*VDD_BT Atheros Communications, Inc. ATHEROS CONFIDENTIALAR6102 ROCm® Data Sheet•23 June 2009•234.2SDIO/GSPI Interface Timing Figure4-2 shows the write timing for a SDIO style transaction. fPPClocktTHLtWLtTLHtISUtWHtIHVIHVILVIHVILVOHVOLInputOutputshaded areas not validtO_DLY (max)tO_DLY (min)Figure4-2. SDIO Timing Table4-2 shows the values for timing constraints for SDIO. Table4-2. SDIO Timing Constraints Parameter fPPtWLtWHtTLHtTHLtISUtIH Description Clock low timeClock high timeClock rise timeClock fall time Clock frequency data transfer mode AehtsrooC nfneidMin 01010--55 -- latiUnit MHznsnsnsnsnsnsnsns Max 25 Note 100 pF ≥ CL (7 cards)100 pF ≥ CL (7 cards)100 pF ≥ CL (7 cards)100 pF ≥ CL (10 cards)100 pF ≥ CL (7 cards)25 pF ≥ CL (1 card)25 pF ≥ CL (1 card)25 pF ≥ CL (1 card)25 pF ≥ CL (1 card) 1010--1450 Input setup timeInput hold time tO_DLY (min)Output delay time during data transfer mode0tO_DLY (max)Output delay time during identification mode0 24 24•AR6102 ROCm® Data SheetJune 2009Atheros Communications, Inc. ATHEROS CONFIDENTIAL 5.Application Guidelines 5.1Typical 11b/g Application For applications that require only 802.11b/g single-antenna operation without the need for cellular and/or Bluetooth coexistence, the AR6102 can be used with a minimal number of external passive components. This is especially advantageous for low-cost, small form-factor consumer electronics devices such as PMPs, PNDs, gaming devices, and cameras. See Figure5-1 for details. This design is the basis of the implementations in subsequent sections.Table5-1 shows the minimum RBOM for typical 11b/g application. 5.2Application Schematic htAorefnoCs neidlatiFigure5-1. Application Schematic Atheros Communications, Inc. ATHEROS CONFIDENTIALAR6102 ROCm® Data Sheet•25 June 2009•25Table5-1. Minimum RBOM for Typical 11b/g Application Item 123 Qty. 521 Description CapacitorCapacitorAntenna Designator C2, C3, C5, C10, C11C6, C9ANT1 Size 02010201N/A Value 1000pF0.1uFN/A 5.311b/g Application with Cellular Coexistence Filter For those applications that are used in an environment with interference from cellular radios, an external band-pass filter may be used with the AR6102. This filter is installed between the AR6102 RF output port and the antenna. Atheros recommends several filters below, each with different characteristics. Depending on design constraints related to size, insertion loss, or attenuation at certain critical frequency bands, an appropriate filter can be chosen. See Table5-2 for details.Table5-3 shows the AR6102 output spur levels for 15dBm 1Mbps transmit. Table5-2. Recommended Co-existence Bandpass Filters Filter Attenuation (dB) Cellular Frequencies 2.17 GHz1.99 GHz1.91 GHz1.79 GHz824 MHzInsertion Loss (dB)Size (L x W x H mm) Murata LFB212G45CE2D006 303040402.7 2.0 x 1.25 x 0.6 Aoreht204040402.5 TDK DEA202450BT-3201B2 C sfno30404040403.0 neidlatiSoshin HMD847H 20404040402.52.0 x 1.25 x 1.0 TDK DEA162450BT-2092AT1-HSoshin HMD844H 12202028301.52.0 x 1.25 x 0.8 Soshin HMD848H 304040403.22.0 x 1.25 x 0.8 2.0 x 1.25 x 0.81.60 x 0.8 x 0.6 2626•AR6102 ROCm® Data SheetJune 2009Atheros Communications, Inc. ATHEROS CONFIDENTIAL Table5-3. Output Spur Levels for 15dBm 1Mbps Transmit Modulated Data Rate 1Mbps Frequency(GHz) 1.8196 1.8461 1.811.9501 2.0021 2.01 2.1061 Spur Level -88.75-83.61-86.8-.56 -94.4 -92.-92.56 5.411b/g Application with Bluetooth-Coexistence The AR6102 supports the standard 2, 3, and 4-wire Bluetooth coexistence handshake protocol. As such, it can easily interface with any 3rd party Bluetooth device which supports this interface. The pins used for each coexistence interface are described in the Figure5-2. htAorefnoCs neidlatiAtheros Communications, Inc. ATHEROS CONFIDENTIALAR6102 ROCm® Data Sheet•27 June 200927Table5-4. Bluetooth Coexistence Interface Pins 2-Wire BT_ACTIVEBT_PRIORITY 3-Wire4-Wire Signals when the BT device is expecting or is currently performing Tx or Rx activity. It remains asserted until the BT device is finished using the medium.Not used. Leave as Asserts when is.current BY activity is high priority (e.e., SCO LMP traffic Time-shared pin: At the start of BT_ACTIVE, it asserts to indicate BT activity priority. Then indicates BT activity, whether it is Tx or Rx BT_FREQ Not used. Leave as Not used. Leave as Indicates whether the BT device is using a is.is.restricted channel occupied by WLAN; signal is only applicable for non-AFH BT devices and provides no benefits if using AFH with WLAN, and/or if BT has low RF isolation from WLAN. The functionality of this pin is made obsolete by the Atheros coexistence scheduler.Indicates whether WLAN grants or blocks BT's Tx/Rx request. The pin polarity is configurable. By default, when asserted, it signals to BT that it has WLAN activity and is blocking BT from using the medium. WLAN_ACTIVE Because the 3-wire interface offers robust coexistence performance and is the most widely adopted, the focus for the implementation will be on this interface. In addition, since most embedded applications utilize a single antenna for WLAN and BT to share, the hardware implementation will focus on the components and control signals that are required for single antenna coexistence. Table5-5. Front End Options - Advantages and Disadvantages Single ANT, with SPDT Advantages Lowest path loss for both WLAN and BT, which allows for highest output power and receive sensitivy. Targeted for higher performance at longer range. No simultaneous WLAN and BT activity, since only one device has access to the antenna at any given time. AorehtC sfnoGiven the single-antenna requirement and the fact that WLAN transmit and receive will occur at one port, the following front-end options are available. These options, along with some high level advantages/disadvantages are summarized in the table below neidlatiDisadvantages 28 28•AR6102 ROCm® Data SheetJune 2009Atheros Communications, Inc. ATHEROS CONFIDENTIAL htAorefnoCs neidlatiFigure5-2. Bluetooth Coexistence Application Atheros Communications, Inc. ATHEROS CONFIDENTIALAR6102 ROCm® Data Sheet•29 June 2009•29It is important to connect the switch control lines such that BT_RF has the antenna when ANTD is HIGH. The reason for this is that when WLAN is asleep or in power-down/reset mode, ANTD defaults to a HIGH and hence allows BT to take control of the medium while WLAN is not being used. Power to the VCC_FEM pins must be continually supplied in each of the operating modes in order to maintain the switch state. While in power-down or power-save mode, the voltage on ANTD ranges from 1.9 - 2.4V across the full range of VCC_FEM (3.0 - 4.2V). Therefore, it is important to select a switch that operates with a switch control voltage between 1.9 - 2.4V in order to allocate the RF path to BT while the WLAN device is in power-down or power-save mode. Figure5-3 depict the major components and signal connections that are necessary for implementing the options summarized in Table5-5. 5.511b/g Application with Antenna Diversity The AR6102 supports fast antenna diversity with the addition of an external SPDT switch and the use of two antennas. A recommended SPDT switch is the NEC uPG2158T5K. To achieve the maximum benefits of antenna diversity, it is recommended to place the antennas as far apart as possible. AorehtC sfnoneidlatiFigure5-3. AR6102 Fast Antenna Diversity Implementation 5.6Power Supply Management The AR6102 requires various power supplies and are described in the table below. The recommended operating conditions for each power supply are also given. It is important to note the current consumption on each supply rail (refer to Table 3-8, 3-9, and 3-10) in order to budget the typical amount of power that needs to be delivered to each supply. Maximum current consumption across temperature and voltage is given in Table5-6. 5.7Supply Ripple Tolerance The maximum ripple that can be tolerated on the VDD18 and 1.2V supplies is 45 mVp-p and 15 mVp-p, respectively. 3030•AR6102 ROCm® Data SheetJune 2009Atheros Communications, Inc. ATHEROS CONFIDENTIAL Table5-6. Power Supplies and Recommended Operating Conditions Symbol VCC_FEM Description / Recommendations ■Supplies internal PA and RF switch controls. ■When using an off-module switch, as in the case for antenna diversity implementations, it is important to make sure that VCC_FEM is at least 100mV higher than the recommended control signal levels of the off-module switch.■Maximum current consumption of 165mA.■Supplies critical analog RF and baseband blocks such as the 2.4GHz Tx/Rx chain, synthesizer, and current reference circuitry. ■Bypass this supply with a 1000pF capacitor placed close to the supply pin. Refer to C2 in Section 5.2 and layout guidelines for details.■Combined VDD_1.2VA and VDD_12 current is 97mA MAX.■Supplies the internal digital logic. ■This can share the same supply as the VDD_1.2VA pin. ■Bypass this supply with a 1000pF capacitor placed close to the supply pin. Refer to C3 in the “Application Schematic” and layout guidelines for details. ■Combined VDD_1.2VA and VDD_12 current is 97mA MAX.■Supplies the BT co-existence I/O interface:BT_Priority / GPIO0 WLAN_ACTIVE / GPIO1BT_FREQ / GPIO2BT_ACTIVE / GPIO3 CLK32K - External 32KHz clock input pin■The voltage for this supply should be set at the same level as the voltage of the I/O interface. ■VDD_BT and sleep clock amplitude should match Min. 3.0 Typ. 3.3 Max 3.6 Unit VDD_1.2VA1.141.21.26 VDD_121.141.21.26 VDD_BT htAorefnoCs neidlati1.8 3.46 1.71 V VDD_GPIO ■Supplies the WAKE_ON_WLAN pin and UART interface pin. ■The voltage for this supply should be set at the same level as the voltage of the I/O interface.■Supplies the SDIO interface, HMODE_1 strap configuration pin, and JTAG interface. ■Voltage level should be set at the same level as the host SDIO interface.■Supplies the RF analog circuitry. ■Bypass this supply with a 1000pF capacitor placed close to the supply pin. Refer to C11 in the and layout guidelines. Refer to C11 in the “Application Schematic” and layout “Application Guidelines” on page25 for details. ■Maximum current consumption of 83mA 1.711.83.46 DVDD_SDIO1.711.83.46 VDD181.711.81. Atheros Communications, Inc.ATHEROS CONFIDENTIALAR6102 ROCm® Data Sheet•31 June 2009315.8Grounding The AR6102 ground pads are not differentiated between digital and analog grounds. As such, all grounds should be connected together on the end application board. 5.9Host Interfaces and GPIOs 5.9.1Secure Digital Input/Output (SDIO) The AR6102 is compliant with SDIO v1.1 specifications. For 4-bit mode, all four SDIO data lines are available. If 1-bit mode is turned on by software, data is sent only over SD_D0; this mode is good for troubleshooting (ie., driver loading issues). The table below describes the SDIO mode pins. Table5-7. SDIO Mode Pins Pin Name SD_CLK SDIO Type I Pad Power SupplyDescription SDIO input clock from Host (up to 25MHz). No external pull-up resistor needed. SD_CmdI/O DVDD_SDIO SD_D0I/O SD_D1I/O SD_D2 SD_D3 AI/O orehtC sfnoneidSDIO Command Line Internal pull-up, no external pull-up resistor needed. SDIO Data0 Line Internal pull-up, no external pull-up resistor needed. SDIO Data1 Line Internal pull-up, no external pull-up resistor needed. SDIO Data2 Line Internal pull-up, no external pull-up resistor needed. SDIO Data3 Line Internal pull-up, no external pull-up resistor needed. latiI/O 5.9.2Dedicated Function Pins ■BT Coexistence ■Wake-on-Wireless –Dedicated to WLAN-BT coexistence using a four-wire bus: BT_PRIORITYWLAN_ACTIVEBT_FREQBT_ACTIVE ■Sleep Clock –Dedicated for wake-on-wireless feature (WAKE_ON_WLAN), a hardware toggle point from the WLAN device to the HOST. Generally, once the system (and thus the WLAN device) is placed into a low-power state, the WLAN device continues to remain associated with its current AP to receive and monitor incoming frames. –If one of a number of specified patters are detected in the frame, the WLAN device wakes up HOST by asserting a hardware pin. Upon wakeup, the driver for the HOST is notified of the change in power state and data connectivity with the AP is re-established. Because this –Dedicated to 32KHz clock input (CLK_32K) ■UART Output –Dedicated to UART Tx (TXD0) 3232•AR6102 ROCm® Data SheetJune 2009Atheros Communications, Inc. ATHEROS CONFIDENTIAL defaults low, the wake-on-wireless interrupt is active high. 5.13Host Configuration Guidelines The option to use SDIO is selected by tying HMODE_1 to the same voltage level as VDD_SDIO. 5.10RF Port Matching The AR6102 uses a single port, LGA pad H1, as an RF input/output for receive/transmit operation. No external DC-block is necessary.For optimal performance, all connections to this port, including traces and antennas, should have a 50-ohm impedance. 5.11External 32KHz Sleep Clock Two hardware solutions exist for the 32KHz sleep clock: ■External sleep clock driven by an XO■HOST driven sleep clock The AR6102 has the ability to provide a buffered 26MHz clock on the BT_CLK_OUT pin. Please refer to Table 3-7 for information about the characteristics of this clock. 5.12Clock Sharing To save layout area and BOM, the HOST 32KHz drive option is recommended for use in the end application. When a HOST 32KHz drive or external oscillator is used, the clock should be DC-coupled into the CLK_32K pin.If the sleep clock voltage swing level exceeds that of the DVDD_SDIO voltage, then a 1K-ohm series resistor at the CLK_32K input is necessary. Depending on the drive strength of the clock source, this resistance may need to be lowered to meet the rise time requirements. htAorefnoCs neidlatiThe buffered clock that is driven out on BT_CLK_OUT is enabled by driving BT_CLK_EN to 1.8V. It is enabled using this signal only and can be enabled regardless of the power state of the AR6102 (power-down mode, sleep and awake modes). As long as the VDD_1.2VA and VDD18 supplies are given to the device and the BT_CLK_EN is driven high, the buffered clock output will be available.There is a minimal current consumption penalty when enabling this clock. Typically, there will be an additional 490uA of current on the VDD18 supply and an additional 458uA on the VDD_1.2VA supply (regardless of operating mode) when the buffered clock is enabled. Atheros Communications, Inc.ATHEROS CONFIDENTIALAR6102 ROCm® Data Sheet•33 June 2009335.14Layout Guidelines 5.14.1General Guidelines A cost effective design can be realized by utilizing vias formed with a 6 mil drill, 11 mil pad, with 2.5 mil angular ring; these can be used to route the 0.35 x 0.35 pads on other layers. The figure below depicts an example of the via placement and escape routes used for each of the inner pads. AorehtC sfnoneidlatiFigure5-4. Layout Diagram In general, the AR6102 can be routed on a 4-layer board assuming the following layer usage: Layer 1: Signals and RF traces. Layer 2: Mainly ground with some signals. RF traces on layer 1 should traverse over solid ground planes on layer 2.Layer 3: Power planesLayer 4: More signals components on the backside of the board is fine, as long as the physical distance to the supply pin is reduced. Supplies that share a regulator need to have bypass capacitors placed close to the AR6102 and prior to the traces joining. 5.15VDD_12 and VDD_1.2VA Power Trace Routing It is critical to route the VDD_12 and VDD_1.2VA supplies using separate traces. Each trace should have a bypass capacitor placed close to the power supply input pin. The traces should only be connected at a central, noise-free node in a star configuration. 5.14.2Component Placement All bypass capacitors depicted in the reference schematic need to be place as close as possible to the AR6102. Placing these bypass 3434•AR6102 ROCm® Data SheetJune 2009Atheros Communications, Inc. ATHEROS CONFIDENTIAL See Figure5-5 for details. Bypassing these two supplies separately is required for optimal EVM and spectrum mask performance. htAorefnoCs neidlatiFigure5-5. Recommended Star Configuration 5.15.3Host Interface Layout For the layout of the host interface signals SD_CLK, SD_CMD, and SD_D[3:0], the following should be checked: ■Verify that GND with uniform vias between ■If the AR6102 is to be used on a the top and bottom layers is incorporated between the CLK line and the data line(s). ■Avoid connections on data and clock lines development platform, it is recommended to incorporate an extra RC filter on the SD_CLK line or other data lines. This is to allow tenability against different hosts which may require different overshoot handling due to length of the interface traces. Keep capacitor values in the RC filter to a minimal value. due to high speed digital voltage returns and inductive characteristics of vias (which can also incorporate capacitive characteristics due to layer to layer capacitance). 5.15.432KHz Clock Signal Layout For an optimal sleep clock signal layout, the designer must keep the clock trace away from digital and power traces. Atheros Communications, Inc.ATHEROS CONFIDENTIALAR6102 ROCm® Data Sheet•35 June 2009•355.15.5Grounding The layout designer must avoid ground discontinuity. RF traces should have solid grounding directly under the entire trace for proper impedance control. AorehtC sfnoneidlati36 36•AR6102 ROCm® Data SheetJune 2009Atheros Communications, Inc. ATHEROS CONFIDENTIAL 6.Assembly Guidelines 6.1Reflow profile Figure6-1 shows the Reflow Profile. See Table6-1 for the recommended reflow settings. [Temp/ °C] Time from 25° C to peak < 220 sec221° C /° CsecPeak temp241-251° C 3~4°C/sec 2~ 11.5~3° C/sec 50° C Pre-heating zone 93-186 sec 25° C 8-16 sec Reflowzone 30-60 sec htA93-186 sec ore85-170 sec noC sdifenlatiCooling zone 60 sec [Time/sec] Figure6-1. Reflow Profile Table6-1. Recommended Reflow Settings Zone Dry Zone Temp ° C Time(sec) 25-5090 Pre-heat ZoneReflow Zone50-22165 22145 Peak Zone241-2512 Cooling217-5060 AtmosphereN2 6.2Solder material recommendations Manufacturer name: Kester Solder paste part number: EM808-Sn96.5% Ag3.0% Cu0.5% SAC305 alloy with Type 3 power, water soluble solder paste Atheros Communications, Inc.ATHEROS CONFIDENTIALAR6102 ROCm® Data Sheet•37 June 200937AorehtC sfnoneidlati38 38•AR6102 ROCm® Data SheetJune 2009Atheros Communications, Inc. ATHEROS CONFIDENTIAL 7.Package Marking Information The chapter explains the package marking on the AR6102. See Figure7-1 for details. Pad A1 IdentifierAtheros ROCm logo with registered ® trademarkROCmLot #Assembled in year YY and work week WW®Device #ATHEROS®AR6102G – 1M2EE08283.1CYYWWlaPHILIPPINESntiFigure7-1. AR6102 Package Marking Country of OriginhtAorenoC sedfiAtheros Communications, Inc. ATHEROS CONFIDENTIALAR6102 ROCm® Data Sheet•39 June 2009•39AorehtC sfnoneidlati40 40•AR6102 ROCm® Data SheetJune 2009Atheros Communications, Inc. ATHEROS CONFIDENTIAL 8.Ordering Information Please contact your local Atheros sales representative at one of the worldwide offices listed below. Atheros Communications, Inc.80 Great America ParkwaySanta Clara, CA 950t +1 408.773.5200f +1 408.773.9940 info@atheros.com Atheros Communications Irvine8 HughesIrvine, Ca. 92618t 949.453.2727 f 949.341.0423 info@atheros.com Atheros LimitedN.T., t +852 8206.1131f +852 8206.1301 Atheros Communications KK-JapanKDX Shinbashi Bldg. 2-9, 2-chome Shinbashi, Minato-ku,Tokyo 105-0004, Japant +81 3.5501.4100f +81 3.5501.4129 sales_japan@atheros.comAtheros Korea 1218, 12F, Downtown Bldg., 22-3 SuNae-dong, Bundang-ku, Seongnam City, Gyeonggi-do, Korea 463-825t +82 31.786.0428 sales_korea@atheros.com Atheros Technology Taiwan Corporation P.O. Box No. 333, Fo Tan Post Office, sales_china@atheros.com AehtsrooC nfneid9F, No.110, Chou Tze St, Nei Hu Dist,Taipei, Taiwan 114 R.O.C.t + 886 2.8751.6385f + 886 2.8751.6397 sales_tw@atheros.com latiAtheros (Shanghai) Co., Ltd.690 Bibo Road,4F,Unit 9Shanghai,P.R.China 201203 t +86-21.5080.3680 f +86 21.5027.0100 sales_china@atheros.comAtheros GmbHBraunschweiger Str. 845886 GelsenkirchenGermany Amy.Chang@atheros.com Atheros Communications, Inc. ATHEROS CONFIDENTIALAR6102 ROCm® Data Sheet•41 June 200941The information in this document has been carefully reviewed and is believed to be accurate. Nonetheless, this document is subject to change without notice. Atheros assumes no responsibility for any inaccuracies that may be contained in this document, and makes no commitment to update or to keep current the contained information, or to notify a person or organization of any updates. Atheros reserves the right to make changes, at any time, to improve reliability, function or design and to attempt to supply the best product possible. MKG-0942 Rev. 2 Atheros Communications, Incorporated80 Great America ParkwaySanta Clara, CA 950t: 408/773-5200f: 408/773-9940www.atheros.com ATHEROS CONFIDENTIALSubject to Change without Notice 因篇幅问题不能全部显示，请点此查看更多更全内容
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