HEF4070B

File under Integrated Circuits, IC04

January 1995

Philips SemiconductorsProduct specification

Quadruple exclusive-OR gate

DESCRIPTION

The HEF4070B provides the positive quadruple

exclusive-OR function. The outputs are fully buffered forhighest noise immunity and pattern insensitivity of outputimpedance.

HEF4070B

gates

Fig.2 Pinning diagram.HEF4070BP(N):14-lead DIL; plastic

(SOT27-1)

HEF4070BD(F):14-lead DIL; ceramic (cerdip)

(SOT73)

HEF4070BT(D):14-lead SO; plastic

(SOT108-1)

Fig.1 Functional diagram.( ): Package Designator North America

Fig.3 Logic diagram (one gate).APPLICATION INFORMATION

Some examples of applications for the HEF4070B are:•Logical comparators

•Parity checkers and generators

FAMILY DATA, IDDLIMITScategory GATESSee Family Specifications

TRUTH TABLEI1LHLHNote

1.H=HIGH state (the more positive voltage)

L=LOW state (the less positive voltage)

I2LLHHO1LHHLJanuary 19952

Philips SemiconductorsProduct specification

Quadruple exclusive-OR gate

AC CHARACTERISTICS

VSS=0 V; Tamb=25°C; CL=50 pF; input transition times≤20 ns

VDDVPropagation delaysIn→OnHIGH to LOW510155LOW to HIGHOutput transition timesHIGH to LOW1015510155LOW to HIGH1015 tTLHtTHL tPLHtPHL8535307530256030206030201757555150655012060401206040nsnsnsnsnsnsnsnsnsnsnsns58 ns24 ns21 ns48 ns19 ns17 ns10 ns9 ns6 ns10 ns9 ns6 ns++++++++++++SYMBOLTYP.MAX.HEF4070B

gates

TYPICAL EXTRAPOLATIONFORMULA(0,55 ns/pF) CL(0,23 ns/pF) CL(0,16 ns/pF) CL(0,55 ns/pF) CL(0,23 ns/pF) CL(0,16 ns/pF) CL(1,0 ns/pF) CL(0,42 ns/pF) CL(0,28 ns/pF) CL(1,0 ns/pF) CL(0,42 ns/pF) CL(0,28 ns/pF) CLVDDVDynamic powerdissipation perpackage (P)51015TYPICAL FORMULA FOR P (µW)1100 fi+∑(foCL)×VDD24900 fi+∑(foCL)×VDD214 400 fi+∑(foCL)×VDD2wherefi=input freq. (MHz)fo=output freq. (MHz)CL=load capacitance (pF)∑(foCL)=sum of outputsVDD=supply voltage (V)January 19953