元器件交易网www.cecb2b.comPhilips Semiconductors Product specification8-bit bus interface latch with set and reset(3-State)74ABT845FEATURESDESCRIPTION•High speed parallel latchesThe 74ABT845 consists of eight D-type latches with 3-State outputs.•In addition to the LE, OE, MR and PRE pins, the 74ABT845 has twoIdeal where high speed, light loading, or increased fan-in areadditional OE pins, making a total of three Output Enable (OE0,required with MOS microprocessorsOE1, OE2) pins. The multiple Output enables allow multiuser control•Broadside pinoutof the interface, e.g., CS, DMA, and RD/WR.•Output capability: +64mA/–32mA•Power-up 3-State•Power-up reset•Latch-up protection exceeds 500mA per Jedec Std 17•ESD protection exceeds 2000 V per MIL STD 883 Method 3015and 200 V per Machine ModelQUICK REFERENCE DATASYMBOLPARAMETERCONDITIONSTamb = 25°C; GND = 0VTYPICALUNITtPropagation delaytPLHPHLDn to QnCL = 50pF; VCC = 5V5.4nsCINInput capacitanceVI = 0V or VCC4pFCOUTOutput capacitanceOutputs disabled; VO = 0V or VCC7pFICCZTotal supply currentOutputs disabled; VCC = 5.5V500nAORDERING INFORMATIONPACKAGESTEMPERATURE RANGEOUTSIDE NORTH AMERICANORTH AMERICADWG NUMBER24-Pin Plastic DIP–40°C to +85°C74ABT845 N74ABT845 NSOT222-124-Pin plastic SO–40°C to +85°C74ABT845 D74ABT845 DSOT137-124-Pin Plastic SSOP Type II–40°C to +85°C74ABT845 DB74ABT845 DBSOT340-124-Pin PlasticTSSOP Type I–40°C to +85°C74ABT845 PW74ABT845PW DHSOT355-1PIN CONFIGURATIONPIN DESCRIPTIONPIN NUMBERSYMBOLFUNCTIONOE0124VCC1, 2, 23OE0 – OE2Output enable inputs(active-Low)OE1223OE23, 4, 5, 6,D0322Q07, 8, 9, 10D0-D7Data inputsD1421Q122, 21, 20, 19,18,Q0-Q7Data outputsD2520Q217, 16, 15D3619Q311MRMaster reset input (active-Low)D4718Q413LELatch enable inputD5817Q5(active-High)D6916Q614PREPreset input (active-Low)D71015Q712GNDGround (0V)MR1114PRE24VCCPositive supply voltageGND1213LETOP VIEWSA002581995 Sep 061853-1703 15702元器件交易网www.cecb2b.comPhilips Semiconductors Product specification8-bit bus interface latch with set and reset(3-State)74ABT845LOGIC SYMBOL (IEEE/IEC)LOGIC SYMBOL1&24567891023EN31411S2D0D1D2D3D4D5D6D713R13LEC114PRE11MR31OE041D222212OE152023OE2619Q0Q1Q2Q3Q4Q5Q6Q771881722212019181716159161015SA00260SA00259FUNCTION TABLEINPUTSOUTPUOPERATINGH=High voltage levelTSMODEh=High voltage level one set-up time prior to the High-to-Low LEOEPRtransitionnEMRLEDnQnL=Low voltage levell=Low voltage level one set-up time prior to the High-to-Low LELLXXXHPresettransitionLHLXXLClearNC=No changeX=Don’t careLHHHLLZ=High impedance “off” stateLHHHHHTransparent↓=High-to-Low transitionLHH↓lLLHH↓hHLatchedHXXXXZHigh impedanceLHHLXNCHoldLOGIC DIAGRAMD0D1D2D3D4D5D6D734567891014PREDPDPDPDPDPDPDPDPLCQLCQLCQLCQLCQLCQLCQLCQ11MR13LEOE012OE1OE2232221201918171615Q0Q1Q2Q3Q4Q5Q6Q7SA002611995 Sep 062元器件交易网www.cecb2b.comPhilips Semiconductors Product specification8-bit bus interface latch with set and reset(3-State)74ABT845ABSOLUTE MAXIMUM RATINGS1,2SYMBOLPARAMETERCONDITIONSRATINGUNITVCCDC supply voltage–0.5 to +7.0VIIKDC input diode currentVI < 0–18mAVIDC input voltage3–1.2 to +7.0VIOKDC output diode currentVO < 0–50mAVOUTDC output voltage3output in Off or High state–0.5 to +5.5VIOUTDC output currentoutput in Low state128mATstgStorage temperature range–65 to 150°CNOTES:1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of thedevice at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure toabsolute-maximum-rated conditions for extended periods may affect device reliability.2.The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junctiontemperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.3.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.RECOMMENDED OPERATING CONDITIONSSYMBOLPARAMETERLIMITSUNITMinMaxVCCDC supply voltage4.55.5VVIInput voltage0VCCVVIHHigh-level input voltage2.0VVILLow-level input voltage0.8VIOHHigh-level output current–32mAIOLLow-level output current64mA∆t/∆vInput transition rise or fall rate05ns/VTambOperating free-air temperature range–40+85°C1995 Sep 063元器件交易网www.cecb2b.comPhilips Semiconductors Product specification8-bit bus interface latch with set and reset(3-State)74ABT845DC ELECTRICAL CHARACTERISTICSLIMITSSYMBOLPARAMETERTEST CONDITIONSTamb = +25°CTamb = –40°Cto +85°CUNITMinTypMaxMinMaxVIKInput clamp voltageVCC = 4.5V; IIK = –18mA–0.9–1.2–1.2VVCC = 4.5V; IOH = –3mA; VI = VIL or VIH2.52.92.5VVOHHigh–level output voltageVCC = 5.0V; IOH = –3mA; VI = VIL or VIH3.03.43.0VVCC = 4.5V; IOH = –32mA; VI = VIL or VIH2.02.42.0VVOLLow–level output voltageVCC = 4.5V; IOL = 64mA; VI = VIL or VIH0.420.550.55VVRSTPower-up output lowvoltage3VCC = 5.5V; IO = 1mA; VI = GND or VCC0.130.550.55VIIInput leakage currentVCC = 5.5V; VI = GND or 5.5V±0.01±1.0±1.0µAIOFFPower-off leakage currentVCC = 0.0V; VO or VI ≤4.5V±5.0±100±100µAIPU/PDPower-up/down V3-state output current4CC = 2.1V; VO = 0.5V; VOE = VCC; VI = GND or VCC±5.0±50±50µAIOZH3-State output High currentVCC = 5.5V; VO = 2.7V; VI = VIL or VIH5.05050µAIOZL3-State output Low currentVCC = 5.5V; VO = 0.5V; VI = VIL or VIH–5.0–50–50µAICEXOutput High leakage currentVCC = 5.5V; VO = 5.5V; VI = GND or VCC5.05050µAIOOutput current1VCC = 5.5V; VO = 2.5V–50–80–180–50–180mAICCHVCC = 5.5V; Outputs High, VI = GND or VCC0.5250250µAICCLQuiescent supply currentVCC = 5.5V; Outputs Low, VI = GND or VCC243030mAICCZVVCC = 5.5V; Outputs 3-State;I = GND or VCC0.5250250µA∆ICCAdditional supply current perVinput pin2CC = 5.5V; one input at 3.4V, other inputs at VCC or GND0.51.51.5mANOTES:1.Not more than one output should be tested at a time, and the duration of the test should not exceed one second.2.This is the increase in supply current for each input at 3.4V.3.For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.4.This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. For VCC = 2.1V to VCC = 5V \" 10%, atransition time of up to 100µsec is permitted.1995 Sep 064元器件交易网www.cecb2b.comPhilips Semiconductors Product specification8-bit bus interface latch with set and reset(3-State)74ABT845AC CHARACTERISTICSGND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500ΩLIMITSSYMBOLPARAMETERWAVEFORMTamb = +25oCTamb = -40 toVCC = +5.0V+85oCUNITVCC = +5.0V ±0.5VMinTypMaxMinMaxtPropagation delay3.95.41.06.2tPLHPHLDn to Qn11.02.25.46.82.27.8nstPropagation delay2.05.16.62.07.5tPLHPHLLE to Qn22.86.47.92.88.9nstPropagation delay2.24.96.62.27.8tPLHPHLPRE to Qn13.05.36.83.07.4nstPropagation delay2.44.96.42.47.3tPLHPHLMR to Qn13.15.97.33.18.5nstOutput enable time41.03.85.41.06.3tPZHPZLOEn to Qn52.04.76.12.06.7nstOutput disable time41.94.66.21.97.2tPHZPLZOEn to Qn52.24.76.42.27.0nsAC SETUP REQUIREMENTSGND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500ΩLIMITSSYMBOLPARAMETERWAVEFORMTTVamb = +25oCamb = -40 to +85oCCC = +5.0VVCC = +5.0V ±0.5VUNITMinTypMints(H)Setup time, High or Low2.81.02.8ts(L)Dn to LE33.51.43.5nstHold time, High or Low1.0–1.21.0th(H)h(L)Dn to LE31.0–0.61.0nstw(H)LE pulse width, High33.01.53.0nstw(L)PRE pulse width, Low63.52.03.5nstw(L)MR pulse width, Low62.81.32.8nstrecPRE recovery time63.01.43.0nstrecMR recovery time63.41.63.4ns1995 Sep 065元器件交易网www.cecb2b.comPhilips Semiconductors Product specification8-bit bus interface latch with set and reset(3-State)AC WAVEFORMSNOTE: For all waveforms, VM = 1.5V.PREVMVMMR, DntPLHtPHLQnVMVMSA00254Waveform 1. Propagation Delay, Data to Output,Preset to Output, and Master Reset to OutputDnVMVMVMVMts(H)th(H)ts(L)th(L)tw(H)LEVMVMVMNOTE: The shaded areas indicate when the input is permittedto change for predictable output performance.SA00256Waveform 3. Data Setup and Hold Times and Latch EnablePulse WidthOEVMVMtPZLtPLZQnVMVOL +0.3VVOLSA00109Waveform 5. 3-State Output Enable Time to Low Level andOutput Disable Time from Low Level1995 Sep 0674ABT845DnLEVMVMtPLHtPHLQnVMVMSA00255Waveform 2. Propagation Delay, Latch Enableto OutputOEVMVMtPZHtPHZQnVMVOH–0.3V0VSA00066Waveform 4. 3-State Output Enable Time to High Level andOutput Disable Time from High LevelPRE, MRVMVMtw(L)tRECLEVMQnQnSA00257Waveform 6. Master Reset and Preset Pulse Width and MasterReset and Preset to Latch Enable Recovery Time6元器件交易网www.cecb2b.comPhilips Semiconductors Product specification8-bit bus interface latch with set and reset(3-State)74ABT845TEST CIRCUIT AND WAVEFORMVCC90%tW90%AMP (V)7.0VNEGATIVEVVPULSEMM10%10%VPULSEINVOUTRL0VGENERATORD.U.T.tTHL (tF)tTLH (tR)RTCLRLtTLH (tR)tTHL (tF)90%90%AMP (V)POSITIVEPULSEVVTest Circuit for 3-State OutputsMM10%t10%W0VSWITCH POSITIONTESTSWITCHVM = 1.5VtPLZclosedInput Pulse DefinitiontPZLclosedAll otheropenDEFINITIONSINPUT PULSE REQUIREMENTSRFAMILYL =Load resistor; see AC CHARACTERISTICS for value.CAmplitudeRep. RatetWtRtFL =Load capacitance includes jig and probe capacitance;see AC CHARACTERISTICS for value.R74ABT3.0V1MHz500ns2.5ns2.5nsT =Termination resistance should be equal to Zpulse generators.OUT ofSA000121995 Sep 067