DRAM cell arrangement and method for its fabricati

专利名称：DRAM cell arrangement and method for its

fabrication

发明人：Bernd Goebel,Emmerich Bertagnolli申请号：US09/105235申请日：19980626公开号：US06075265A公开日：20000613

摘要：The DRAM cell arrangement has three transistors per memory cell, at least oneof which transistors is designed as a vertical transistor. The transistors may be formed onsidewalls (1F1, 1F2, 2F2) of trenches (G1, G2). In order to fabricate contact regions (K)which respectively connect together three source/drain regions (1 S/D1, 3 S/D2, 2 S/D 2)of different transistors, it is advantageous to arrange the trenches (G1, G2) alternatelywith a larger distance and a smaller distance from one another. Gate electrodes (Ga1,Ga3) of transistors may be formed as parts of writing word lines (WS) or read-out wordlines (WA) in the form of spacers on sidewalls (1F1, 1F2) of the trenches (G1). Connectionsbetween gate electrodes (Ga2) and source/drain regions (3 S/D1) may be made viaconductive structures (L).

申请人：SIEMENS AKTIENGESELLSCHAFT

代理机构：Hill & Simpson

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