COMPILER AND LOGIC CIRCUIT DESIGN METHOD

专利名称：COMPILER AND LOGIC CIRCUIT DESIGN

METHOD

发明人：TANIMOTO, TADAAKI,KAMADA, MASURAO申请号：JP0312839申请日：20031007

公开号：WO20040363A9公开日：20050120

摘要：A compiler is supplied with a pseudo C description (1) which can describeparallel operation at the statement level by a clock boundary and a register assignmentstatement with a cycle accuracy, identifies the register assignment statement (S2),generates an executable C description (3), extracts a state machine in which the numberof states has been reduced, and judges whether any loop executed by 0 cycle is present(S5). If none, the compiler generates a circuit description (4) capable of synthesizing alogic. Thus, a pseudo C description having C description in which a clock boundary isexplicitly inserted is input. Since the pseudo C description capable of parallel descriptionat the statement level by the register assignment statement is input, it is possible toexpress the pipeline operation accompanied by stall operation.

申请人：RENESAS TECHNOLOGY CORP.,TANIMOTO, TADAAKI,KAMADA, MASURAO

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