FPGA可编程逻辑器件芯片XC3S400A-5FGG400C中文规格书

Table 60: TXCRC Attributes (cont'd)

TXCRC Attributes

CRC_EN

[0:0]

CRC Generator Enable.0: Disabled1: Enabled

TX Polarity Control

If the TXP and TXN differential traces are accidentally swapped on the PCB, the differential datatransmitted by the transceiver TX is reversed. One solution is to invert the parallel data beforeserialization and transmission to offset the reversed polarity on the differential pair. The TXpolarity control can be accessed through the CH*_TXPOLARITY input from the interconnectlogic interface. It is driven High to invert the polarity of the outgoing data.

Ports and Attributes

The following table defines the ports required for TX polarity control.Table 61: TX Polarity Control Ports

Port

CH[0/1/2/3]_TXPOLARITY

Direction

Input

Clock Domain

TXUSRCLK

Description

This port is used to invert the polarity ofoutgoing data.

0: Not inverted. TXP is positive, and TXN isnegative.

1: Inverted. TXP is negative, and TXN ispositive.

There are no TX polarity control attributes in Versal ACAPs.

Using TX Polarity Control

CH*_TXPOLARITY can be tied High if the polarity of TXP and TXN needs to be reversed.

TX Fabric Clock Output Control

The TX Clock Divider Control block has two main components: serial clock divider control andparallel clock divider and selector control. The clock divider and selector details are illustrated inthe following figure.

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Chapter 3: Transmitter

Figure 62: TX Serial and Parallel Clock Divider

GTYE5_QUAD (GTY Transceiver Primitive)TX PMATXP/NPISOTX DATATX PCSPolarity ControlTX DATA from Upstream PCS BlocksTXPI_BYPASSTX Phase Interp.01÷D{1,2,4,8,16}000110÷{2,4}÷{4,5,8,10}ILOTX PROG DIVTX_PROGCLK_SEL1010CHCLK_CLKSRCMUX_SELTX_PLLCLK_SELTXOUTPCSCLKTXPHYCLKTXREFCLKPMALCPLLHSCLK0/110REFCLK SELREFCLK SELRPLLTX_DA_REFCLK_SEL0010100111÷2TX DAPITX DADIV0CH*_TXOUTCLKTXPROGDIVCLK101TX DAPIBYPASS DIVTXOUTCLKCTLTXOUTCLK_PREDAPITX_DA_BYPREFCLK DistributionIBUFDS_GTE5OMGTREFCLKNODIV2Output Clock to BUFG_GTOutput to GTYE5_QUADMGTREFCLKPREFCLK_HROW_CK_SELX21390-031121Note:

1.CH*_TXOUTCLK is used as the source of the interconnect logic clock via BUFG_GT.

The RPLL and LCPLL from HSCLK0 can only be used by TX channel 0/1, and RPLL and LCPLL fromHSCLK1 can only be used by TX channel 2/3.

2.The selection of the /2 and /4 divider block and /4, /5, /8, and /10 divider block is selected based on

the TX_DATA_WIDTH and TX_INT_DATA_WIDTH.3.For details about placement constraints and restrictions on clocking resources (such as BUFG_GT and

BUFG_GT_SYNC), refer to the Versal ACAP Clocking Resources Architecture Manual (AM003).4.The clock output from IBUFDS_GTE5 should only be used after GTPOWERGOOD asserts High.

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Chapter 3: Transmitter

Serial Clock Divider

Each transmitter PMA module has a D divider that divides down the clock from the PLL for lowerline rate support. This serial clock divider, D, can be set statically for applications with a fixed linerate or it can be changed dynamically for protocols with multiple line rates.

To use the D divider in fixed line rate applications, TXOUT_DIV must be set to the appropriatevalue, and the CH*_TXRATE port should be tied to 8'b00000000.

For multiple line rate applications, the CH*_TXRATE port is used to dynamically select the linerate settings which include the appropriate divider values. See Rate Change for more details.

Parallel Clock Divider and Selector

The parallel clock outputs from the TX clock divider control block can be used as an interconnectlogic clock, depending on the line rate requirement.

The recommended clock for the interconnect logic is the CH*_TXOUTCLK from one of the GTY/GTYP transceivers. It is also possible to bring the MGTREFCLK directly to the interconnect logicand use it as the interconnect logic clock. CH*_TXOUTCLK is preferred for general applicationsbecause it has an output delay control used for applications that bypass the TX buffer for outputlane deskewing or constant datapath delay. Refer to TX Buffer Bypass for more details.TXOUTCLKCTL controls the input selector and allows these clocks to be output via theCH*_TXOUTCLK port:

•3'b001: TXOUTPCSCLK path is not recommended to be used because it incurs extra delayfrom the PCS block.•3'b010: TXPHYCLK is the divided down PLL clock after the TX phase interpolator and isused by the TX PCS block. This clock is interrupted when the PLL is reset by one of therelated reset signals.•3'b011: TXREFCLKPMA is the input reference clock to the RPLL or LCPLL, depending on theTXOUTCLKCTL setting. TXREFCLKPMA is the recommended clock for general usage and isrequired for the TX buffer bypass mode.•3'b101: TXPRODIVCLK is the divided down PLL clock after the TX programmable divider.See TX Programmable Divider for more details.

TX Programmable Divider

The TX programmable divider shown in TX Fabric Clock Output Control uses one of the PLL

output clocks to generate a parallel output clock. By using the transceiver PLL, TX programmabledivider, and BUFG_GT, CH*_TXOUTCLK (TXOUTCLKSEL = 101) can be used as a clock sourcefor the interconnect logic. The supported divider values are 4, 5, 5.5, 8, 10, 16, 16.5, 20, 32, 33,and 40.

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Versal ACAP GTY and GTYP Transceivers Architecture Manual