AD7192BRUZ;AD7192BRUZ-REEL;中文规格书,Datasheet资料

4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA

AD7192

Temperature measurement Chromatography

PLC/DCS analog input modules Data acquisition

Medical and scientific instrumentation

FEATURES

RMS noise: 11 nV @ 4.7 Hz (gain = 128) 15.5 noise-free bits @ 2.4 kHz (gain = 128) Up to 22 noise-free bits (gain = 1) Offset drift: 5 nV/°C Gain drift: 1 ppm/°C Specified drift over time

2 differential/4 pseudo differential input channels Automatic channel sequencer Programmable gain (1 to 128)

Output data rate: 4.7 Hz to 4.8 kHz Internal or external clock

Simultaneous 50 Hz/60 Hz rejection 4 general-purpose digital outputs Power supply

AVDD: 3 V to 5.25 V DVDD: 2.7 V to 5.25 V Current: 4.35 mA

Temperature range: –40°C to +105°C Package: 24-lead TSSOP

GENERAL DESCRIPTION

The AD7192 is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC). The on-chip low noise gain stage means that signals of small amplitude can be interfaced directly to the ADC.

The device can be configured to have two differential inputs or four pseudo differential inputs. The on-chip channel sequencer allows several channels to be enabled, and the AD7192 sequentially converts on each enabled channel. This simplifies communication with the part. The on-chip 4.92 MHz clock can be used as the clock source to the ADC or, alternatively, an external clock or crystal can be used. The output data rate from the part can be varied from 4.7 Hz to 4.8 kHz.

The device has two digital filter options. The choice of filter affects the rms noise/noise-free resolution at the programmed output data rate, the settling time, and the 50 Hz/60 Hz rejection. For applications that require all conversions to be settled, the AD7192 includes a zero latency feature.

The part operates with a power supply from 3 V to 5.25 V. It consumes a current of 4.35 mA. It is housed in a 24-lead TSSOP package.

INTERFACE

3-wire serial

SPI, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on SCLK

APPLICATIONS

Weigh scales

Strain gage transducers Pressure measurement

AGNDAVDDFUNCTIONAL BLOCK DIAGRAM

DVDDDGNDREFIN1(+)REFIN1(–)REFERENCEDETECTAIN1AIN2AIN3AIN4AINCOMAVDDAD7192MUXPGAΣ-ΔADCSERIALINTERFACEANDCONTROLLOGICDOUT/RDYDINSCLKCSSYNCAGNDBPDSWTEMPSENSORCLOCKCIRCUITRYP3P2MCLK1MCLK2P0/REFIN2(–)P1/REFIN2(+)07822-001AGND

Figure 1.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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AD7192

TABLE OF CONTENTS

Features .............................................................................................. 1 Interface ............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ..................................................................... 7 Circuit and Timing Diagrams ..................................................... 7 Absolute Maximum Ratings ............................................................ 9 Thermal Resistance ...................................................................... 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 12 RMS Noise and Resolution ............................................................ 14 Sinc4 Chop Disabled ................................................................... 14 Sinc3 Chop Disabled ................................................................... 15 Sinc4 Chop Enabled .................................................................... 16 Sinc3 Chop Enabled .................................................................... 17 On-Chip Registers .......................................................................... 18 Communications Register ......................................................... 18 Status Register ............................................................................. 19 Mode Register ............................................................................. 19 Configuration Register .............................................................. 21 Data Register ............................................................................... 23 ID Register ................................................................................... 23 GPOCON Register ..................................................................... 24

Offset Register ............................................................................ 24 Full-Scale Register ...................................................................... 24 ADC Circuit Information .............................................................. 25 Overview ..................................................................................... 25 Filter, Output Data Rate, and Settling Time ........................... 25 Digital Interface .......................................................................... 28 Circuit Description......................................................................... 32 Analog Input Channel ............................................................... 32 Programmable Gain Array (PGA) ........................................... 32 Bipolar/Unipolar Configuration .............................................. 32 Data Output Coding .................................................................. 32 Clock ............................................................................................ 32 Burnout Currents ....................................................................... 33 Reference ..................................................................................... 33 Reference Detect ......................................................................... 33 Reset ............................................................................................. 34 System Synchronization ............................................................ 34 Temperature Sensor ................................................................... 34 Bridge Power-Down Switch ...................................................... 34 Logic Outputs ............................................................................. 34 Enable Parity ............................................................................... 35 Calibration ................................................................................... 35 Grounding and Layout .............................................................. 36 Applications Information .............................................................. 37 Weigh Scales ................................................................................ 37 Outline Dimensions ....................................................................... 38 Ordering Guide .......................................................................... 38

REVISION HISTORY

5/09—Rev. 0 to Rev. A

Change to Gain Error Specification ............................................... 3 Changes to Table 3 ............................................................................ 9 5/09—Revision 0: Initial Version

Rev. A | Page 2 of 40

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AD7192

SPECIFICATIONS

AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFINx(+) = AVDD, REFINx(−) = AGND, MCLK = 4.92 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1.

Parameter AD7192B Unit Test Conditions/Comments1 ADC Output Data Rate 4.7 to 4800 Hz nom Chop disabled 1.17 to 1200 Hz nom Chop enabled, sinc4 filter 1.56 to 1600 Hz nom Chop enabled, sinc3 filter No Missing Codes2 24 Bits min FS > 1, sinc4 filter3 24 Bits min FS > 4, sinc3 filter3 Resolution See the RMS Noise and Resolution section RMS Noise and Output Data Rates See the RMS Noise and Resolution section Integral Nonlinearity

2

Gain = 1 ±10 ppm of FSR max ±2 ppm typical, AVDD = 5 V ±15 ppm of FSR max ±2 ppm typical, AVDD = 3 V Gain > 1 ±30 ppm of FSR max ±5 ppm typical, AVDD = 5 V ±30 ppm of FSR max ±12 ppm typical, AVDD = 3 V

4, 5

Offset Error ±150/gain μV typ Chop disabled ±0.5 μV typ Chop enabled Offset Error Drift vs. Temperature ±150/gain nV/°C typ Gain = 1 to 16; chop disabled ±5 nV/°C typ Gain = 32 to 128; chop disabled ±5 nV/°C typ Chop enabled Offset Error Drift vs. Time 25 nV/1000 hours typ Gain > 32 Gain Error4 ±0.001 % typ AVDD = 5 V, gain = 1, TA = 25°C (factory

calibration conditions)

−0.39 % typ Gain = 128, before full-scale calibration (see

Table 23)

±0.003 % typ Gain > 1, after internal full-scale calibration,

AVDD ≥ 4.75 V.

±0.005 % typ Gain > 1, after internal full-scale calibration,

AVDD < 4.75 V

Gain Drift vs. Temperature ±1 ppm/°C typ Gain Drift vs. Time 10 ppm/1000 hours typ Gain = 1. Power Supply Rejection 90 dB typ Gain = 1, VIN = 1 V. 95 dB min Gain > 1, VIN = 1 V/gain, 110 dB typ. Common-Mode Rejection

2

@ DC 100 dB min Gain = 1, VIN = 1 V. @ DC 110 dB min Gain > 1, VIN = 1 V/gain.

2

@ 50 Hz, 60 Hz 120 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. @ 50 Hz, 60 Hz2 120 dB min 50 ± 1 Hz (50 Hz output data rate), 60 ± 1 Hz

(60 Hz output data rate).

2

Normal Mode Rejection

4

FSincilter

Internal Clock @ 50 Hz, 60 Hz 100 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 74 dB min 50 Hz output data rate, REJ606 = 1,

50 ± 1 Hz, 60 ± 1 Hz.

@ 50 Hz 96 dB min 50 Hz output data rate, 50 ± 1 Hz. @ 60 Hz 97 dB min 60 Hz output data rate, 60 ± 1 Hz.

Rev. A | Page 3 of 40

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AD7192

Parameter AD7192B Unit Test Conditions/Comments1

External Clock @ 50 Hz, 60 Hz 120 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 82 dB min 50 Hz output data rate, REJ606 = 1,

50 ± 1 Hz, 60 ± 1 Hz.

@ 50 Hz 120 dB min 50 Hz output data rate, 50 ± 1 Hz. @ 60 Hz 120 dB min 60 Hz output data rate, 60 ± 1 Hz. Sinc3 Filter Internal Clock @ 50 Hz, 60 Hz 75 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 60 dB min 50 Hz output data rate, REJ606 = 1,

50 ± 1 Hz, 60 ± 1 Hz.

@ 50 Hz 70 dB min 50 Hz output data rate, 50 ± 1 Hz. @ 60 Hz 70 dB min 60 Hz output data rate, 60 ± 1 Hz. External Clock @ 50 Hz, 60 Hz 100 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 67 dB min 50 Hz output data rate, REJ606 = 1,

50 ± 1 Hz, 60 ± 1 Hz.

@ 50 Hz 95 dB min 50 Hz output data rate, 50 ± 1 Hz. @ 60 Hz 95 dB min 60 Hz output data rate, 60 ± 1 Hz.

ANALOG INPUTS Differential Input Voltage Ranges ± VREF/gain V nom VREF = REFINx(+) − REFINx(−),

gain = 1 to 128.

± (AVDD – 1.25 V)/gain V min/max Gain > 1. Absolute AIN Voltage Limits2 Unbuffered Mode AGND − 50 mV V min AVDD + 50 mV V max Buffered Mode AGND + 250 mV V min AVDD − 250 mV V max Analog Input Current Buffered Mode

2

Input Current ±2 nA max Gain = 1. ±3 nA max Gain > 1. Input Current Drift ±5 pA/°C typ Unbuffered Mode Input Current ±3.5 μA/V typ Gain = 1, input current varies with input

voltage.

±1 μA/V typ Gain > 1. Input Current Drift ±0.05 nA/V/°C typ External clock. ±1.6 nA/V/°C typ Internal clock. REFERENCE INPUT REFIN Voltage AVDD V nom REFIN = REFINx(+) − REFINx(−). 1 V min AVDD V max The differential input must be limited to

±(AVDD – 1.25 V)/gain when gain > 1.

2

Absolute REFIN Voltage Limits GND – 50 mV V min AVDD + 50 mV V max Average Reference Input Current 4.5 μA/V typ

Rev. A | Page 4 of 40

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AD7192

Parameter AD7192B Unit Test Conditions/Comments1 nA/V/°C typ External clock. Average Reference Input Current ±0.03 Drift ±1.3 nA/V/°C typ Internal clock. 2Normal Mode Rejection Same as for analog inputs Common-Mode Rejection 100 dB typ Reference Detect Levels 0.3 V min 0.6 V max TEMPERATURE SENSOR Accuracy ±2 °C typ Applies after user calibration at 25°C. Sensitivity 2815 Codes/°C typ Bipolar mode. BRIDGE POWER-DOWN SWITCH RON 10 Ω max Allowable Current2 30 mA max Continuous current. BURNOUT CURRENTS AIN Current 500 nA nom Analog inputs must be buffered and chop disabled. DIGITAL OUTPUTS (P0 to P3) Output High Voltage, VOH AVDD − 0.6 V min AVDD = 3 V, ISOURCE = 100 μA. Output Low Voltage, VOL 0.4 V max AVDD = 3 V, ISINK = 100 μA. Output High Voltage, VOH 4 V min AVDD = 5 V, ISOURCE = 200 μA. Output Low Voltage, VOL 0.4 V max AVDD = 5 V, ISINK = 800 μA. 2Floating-State Leakage Current ±100 nA max 10 pF typ Floating-State Output Capacitance INTERNAL/EXTERNAL CLOCK Internal Clock Frequency 4.92 ± 4% MHz min/max Duty Cycle 50:50 % typ External Clock/Crystal requency 4.9152 MHz nom 2.4576/5.12 MHz min/max Input Low Voltage VINL 0.8 V max DVDD = 5 V. 0.4 V max DVDD = 3 V. Input High Voltage, VINH 2.5 V min DVDD = 3 V. 3.5 V min DVDD = 5 V. Input Current ±10 μA max LOGIC INPUTS 2Input High Voltage, VINH 2 V min Input Low Voltage, VINL2 0.8 V max 2Hysteresis 0.1/0.25 V min/V max Input Currents ±10 μA max LOGIC OUTPUT (DOUT/RDY) Output High Voltage, VOH2 DVDD − 0.6 V min DVDD = 3 V, ISOURCE = 100 μA. 2Output Low Voltage, VOL 0.4 V max DVDD = 3 V, ISINK = 100 μA. Output High Voltage, VOH2 4 V min DVDD = 5 V, ISOURCE = 200 μA. 2Output Low Voltage, VOL 0.4 V max DVDD = 5 V, ISINK = 1.6 mA. Floating-State Leakage Current ±10 μA max 10 pF typ Floating-State Output Capacitance Data Output Coding Offset binary Rev. A | Page 5 of 40

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AD7192

Parameter

SYSTEM CALIBRATION2

Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span

POWER REQUIREMENTS7 Power Supply Voltage AVDD − AGND DVDD − DGND

Power Supply Currents AIDD Current

DIDD Current

IDD (Power-Down Mode)

12

AD7192B

1.05 × FS −1.05 × FS 0.8 × FS 2.1 × FS

3/5.25 2.7/5.25 0.6 0.85 3.2 3.6 4.5 5 0.4 0.6 1.5 3 Unit

V max V min V min V max

V min/max V min/max

mA max mA max mA max mA max mA max mA max mA max mA max mA typ μA max Test Conditions/Comments1

0.53 mA typical, gain = 1, buffer off. 0.75 mA typical, gain = 1, buffer on. 2.5 mA typical, gain = 8, buffer off. 3 mA typical, gain = 8, buffer on.

3.5 mA typical, gain = 16 to 128, buffer off. 4 mA typical, gain = 16 to 128, buffer on. 0.35 mA typical, DVDD = 3 V. 0.5 mA typical, DVDD = 5 V. External crystal used.

Temperature range: −40°C to +105°C.

Specification is not production tested but is supported by characterization data at initial product release. 3

FS is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. 4

Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full-scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate. 5

The analog inputs are configured for differential mode. 6

REJ60 is a bit in the mode register. When the output data rate is set to 50 Hz, setting REJ60 to 1 places a notch at 60 Hz, allowing simultaneous 50 Hz/60 Hz rejection. 7

Digital inputs equal to DVDD or DGND.

Rev. A | Page 6 of 40

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AD7192

TIMING CHARACTERISTICS

AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted. Table 2. Parameter Limit at TMIN, TMAX (B Version) t3 100 t4 100 READ OPERATION t1 0 60 80 3t2 0 60 80 5, 6t5 10 80 t6 0 t7 10 WRITE OPERATION t8 t9 t10 t11 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. See Figure 3 and Figure 4. 3

These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 4

The SCLK active edge is the falling edge of SCLK. 5

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once.

12

Unit ns min ns min ns min ns max ns max ns min ns max ns max ns min ns max ns min ns min ns min ns min ns min ns min Conditions/Comments1, 2 SCLK high pulse width SCLK low pulse width CS falling edge to DOUT/RDY active time DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V SCLK active edge to data valid delay4 DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V Bus relinquish time after CS inactive edge SCLK inactive edge to CS inactive edge SCLK inactive edge to DOUT/RDY high CS falling edge to SCLK active edge setup time4 Data valid to SCLK edge setup time Data valid to SCLK edge hold time CS rising edge to SCLK edge hold time 0 30 25 0

CIRCUIT AND TIMING DIAGRAMS

ISINK (1.6mA WITH DVDD = 5V,100µA WITH DVDD = 3V)TOOUTPUTPIN50pFISOURCE (200µA WITH DVDD = 5V,100µA WITH DVDD = 3V)07822-0021.6V

Figure 2. Load Circuit for Timing Characterization

Rev. A | Page 7 of 40

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AD7192

CS (I)t1t6t5

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DOUT/RDY (O)MSBLSBt2t7t3SCLK (I)t4I = INPUT, O = OUTPUTFigure 3. Read Cycle Timing Diagram

CS (I)t8t11SCLK (I)t9t10DIN (I)MSBLSB400-2I = INPUT, O = OUTPUT2870Figure 4. Write Cycle Timing Diagram

Rev. A | Page 8 of 40

300-22870

AD7192

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Table 3.

Parameter AVDD to AGND DVDD to AGND AGND to DGND

Analog Input Voltage to AGND Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND AIN/Digital Input Current

Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Lead Temperature, Soldering Reflow

Rating

−0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +0.3 V

−0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to DVDD + 0.3 V 10 mA

−40°C to +105°C −65°C to +150°C 150°C

260°C

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance

Package Type 24-Lead TSSOP

θJA 128

θJC Unit 42 °C/W

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Rev. A | Page 9 of 40

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AD7192

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

MCLK11MCLK22SCLK3CS4P35P26P1/REFIN2(+)7P0/REFIN2(–)8NC9AINCOM10AIN111AIN212242322DINDOUT/RDYSYNCDVDDAVDDDGNDAGNDBPDSWREFIN1(–)REFIN1(+)AIN407822-005AD7192TOP VIEW(Not to Scale)212019181716151413AIN3NC = NO CONNECT

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 MCLK1 When the master clock for the device is provided externally by a crystal, the crystal is connected between MCLK1 and MCLK2. 2 MCLK2 Master Clock Signal for the Device. The AD7192 has an internal 4.92 MHz clock. This internal clock can be made available on the MCLK2 pin. The clock for the AD7192 can be provided externally also in the form of a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock and the MCLK1 pin left unconnected. 3 SCLK Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information transmitted to or from the ADC in smaller batches of data. 4 Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in CS systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. 5 P3 Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and AGND. 6 P2 Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and AGND. 7 P1/REFIN2(+) Digital Output Pin/Positive Reference Input. This pin functions as a general-purpose output bit referenced between AVDD and AGND. When the REFSEL bit in the configuration register = 1, this pin functions as REFIN2(+). An external reference can be applied between REFIN2(+) and REFIN2(−). REFIN2(+) can lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN2(+) − REFIN2(−)), is AVDD, but the part functions with a reference from 1 V to AVDD. 8 P0/REFIN2(−) Digital Output Pin/Negative Reference Input. This pin functions as a general-purpose output bit referenced between AVDD and AGND. When the REFSEL bit in the configuration register = 1, this pin functions as REFIN2(−). This reference input can lie anywhere between AGND and AVDD − 1 V. 9 NC No Connect. This pin should be tied to AGND. 10 AINCOM Analog inputs AIN1 to AIN4 are referenced to this input when configured for pseudodifferential operation. 11 AIN1 Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN2 or as a pseudodifferential input when used with AINCOM. 12 AIN2 Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN1 or as a pseudodifferential input when used with AINCOM. Rev. A | Page 10 of 40

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ANALOG-DEVICESAD7192BRUZ

AD7192BRUZ-REEL