Testing apparatus and testing method

专利名称：Testing apparatus and testing method发明人：Kenichi Fujisaki申请号：US11511854申请日：20060829

公开号：US20070208969A1公开日：20070906

专利附图：

摘要：A testing apparatus according to the present invention includes: a patterngenerator for generating an address signal, a data signal and an expected value signal tobe provided to a memory under test; an OR comparator for outputting fail data when anoutput signal outputted by the memory under test is not matched with the expected

value signal; a first FBM for storing the fail data in a first test; a second FBM foraccumulating the fail data stored in the first FBM and fail data in a second test andstoring therein the same; and a safe analysis section for performing a fail safe analysis onthe memory under test with reference to the fail data stored in the first FBM. The firstFBM accumulates the fail data stored in the second FBM and the fail data in the third test.The safe analysis section performs a fail safe analysis on the memory under test furtherwith reference to the fail data stored in the second FBM.

申请人：Kenichi Fujisaki

地址：Tokyo JP

国籍：JP

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