A63L83361
256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output
Preliminary
Document Title 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output Revision History
0.0
Initial issue
July 14, 2005
Preliminary
Date Remark Rev. No. History Issue PRELIMINARY (July, 2005, Version 0.0)
AMIC Technology, Corp.
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A63L83361
256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output
Preliminary
Features
Fast access times: 6.5/7.5/8.0 ns(153/133/117 MHz) Single 3.3V±5% power supply Synchronous burst function Individual Byte Write control and Global Write Three separate chip enables allow wide range of options for CE control, address pipelining
General Description
The A63L83361 is a high-speed SRAM containing 9M bits of bit synchronous memory, organized as 256K words by 36 bits.
The A63L83361 combines advanced synchronous peripheral circuitry, 2-bit burst control, input registers, output buffer and a 256K X 36 SRAM core to provide a wide range of data RAM applications.
The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. Synchronous inputs include all addresses (A0 - A17), all data inputs (I/O1 - I/O36 ), active LOW chip enable (CE), two additional chip enables (CE2, CE2), burst control inputs (ADSC, ADSP, ADV), byte write enables (BWE, BW1, BW2, BW3, BW4) and Global Write (GW). Asynchronous inputs include output enable (OE), clock (CLK), BURST mode (MODE) and SLEEP mode (ZZ).
Selectable BURST mode
SLEEP mode (ZZ pin) provided Available in 100-pin LQFP package Industrial operating temperature range: -45°C to
+125°C for -I series
Burst operations can be initiated with either the address status processor (ADSP) or address status controller (ADSC) input pin. Subsequent burst sequence burst addresses can be internally generated by the A63L83361 and controlled by the burst advance (ADV) pin. Write cycles are internally self-timed and synchronous with the rising edge of the clock (CLK).
This feature simplifies the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/O1 - I/O9, BW2 controls I/O10 - I/O18, BW3 controls I/O19 - I/O27, and BW4 controls I/O28 - I/O36, all on the condition that BWE is LOW. GW LOW causes all bytes to be written.
PRELIMINARY (July, 2005, Version 0.0) 1
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A63L83361
Pin Configuration
ADSCGNDVCCADSPBWEBW4BW3BW2BW1CLKCE2A6A7ADVCE2GWOECEA8829998979695949392919089888786858483I/O19I/O20I/O21VCCQGNDQI/O22I/O23I/O24I/O25GNDQVCCQI/O26I/O27NCVCCNCGNDI/O28I/O29VCCQGNDQI/O30I/O31I/O32I/O33GNDQVCCQI/O34I/O35I/O36
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495010081A98079787776757473727170696867I/O18I/O17I/O16VCCQGNDQI/O15I/O14I/O13I/O12GNDQVCCQI/O11I/O10GNDNCVCCZZI/O8I/O7VCCQGNDQI/O6I/O5I/O4I/O3GNDQVCCQI/O2I/O1I/O9
A63L83361E66656463626160595857565554535251NCA5A4A3A2A1A0GNDNCMODEVCCNCA10A11A12A13A14A15A16A17
PRELIMINARY (July, 2005, Version 0.0) 2
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ZZ
MODEADV
A63L83361
MODELOGICBlock Diagram
CLK
CLKLOGICADSCADSPBURSTLOGICADDRESSCOUNTERCLRA0-A17ADDRESSREGISTERS189 BYTE1 WRITE DRIVER BYTE2 WRITE DRIVER BYTE3 WRITE DRIVER BYTE4 WRITE DRIVER99GWBWEBW1BW2BW3BW4BYTEWRITEENABLELOGIC99256KX9X4MEMORY36OUTPUTBUFFERARRAY999364DATA-INREGISTERS4CECE2CE2OEI/O1 - I/O36 CHIP ENABLE LOGIC OUTPUT ENABLE LOGIC
PRELIMINARY (July, 2005, Version 0.0) 3
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A63L83361
Symbol Description Pin Description
Pin No. 32 – 37 , 43 - 50, 81, 82, 99, 100 A0 - A17 Address Inputs 89 CLK Clock 87, 93 - 96 88 86 92, 97, 98 83 84 85 31 BWE, BW1 - BW4GW OE CE2,CE2, CE ADV ADSP ADSC MODE Byte Write Enables Global Write Output Enable Chip Enables Burst Address Advance Processor Address Status Controller Address Status Burst Mode: HIGH or NC (Interleaved burst) LOW (Linear burst) Asynchronous Power-Down (Snooze): HIGH (Sleep) LOW or NC (Wake up) 64 ZZ 1,2, 3, 6 - 9, 12, 13, 18, 19, 22 - 25, 28, 29,30,51, 52, 53, 56 - 59, 62, 63, 68, 69, 72 - 75, 78, 79,80 1, 14, 16, 30, 38, 39, 42, 43, 51, 66, 80 15, 41, 65, 91 17, 40, 67, 90 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76
I/O1- I/O36 Data Inputs/Outputs NC No Connection VCC GND VCCQ Power Supply Ground Isolated Output Buffer Supply GNDQ Isolated Output Buffer Ground PRELIMINARY (July, 2005, Version 0.0) 4
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A63L83361
Synchronous Truth Table (See Notes 1 Through 5)
Operation Address I/O CE2CLKADSC WRITECE2CE ADVOE ADSPUsed OperationNONE H X X X L X X X L-H High-Z Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst NONE L X L L X X X X L-H High-Z NONE L H X L X X X X L-H High-Z NONE L X L H L X X X L-H High-Z NONE L H X H L X X X L-H High-Z ExternalExternalExternalExternalExternalL L H L X X X L L-H Dout L L H L X X X H L-H High-Z L L H H L X L X L-H Din L L H H L X H L L-H Dout L L H H L X H H L-H High-Z Next X X X H H L H L L-H Dout Next X X X H H L H H L-H High-Z Next H X X X H L H L L-H Dout Next H X X X H L H H L-H High-Z Next X X X H H L L X L-H Din Next H X X X H L L X L-H Din Current X X X H H H H L L-H Dout Current X X X H H H H H L-H High-Z Current H X X X Current H X X X H H H H H L L-H Dout H H L-H High-Z Din Din Current X X X H H H L X L-H Current H X X X H H L X L-H PRELIMINARY (July, 2005, Version 0.0) 5
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A63L83361
Notes: 1. X = \"Disregard\
WRITE = L means: 2.
BWx (BW1,BW2,BW3, or BW4) and BWE are low or 1) Any GW is low. 2)
3. All inputs except OE must be synchronized with setup and hold times around the rising edge (L-H) of CLK. 4. For write cycles that follow read cycles, OE must be HIGH before the input data request setup time and held HIGH throughout the input data hold time.
ADSP LOW always initiates an internal Read at the L-H edge of CLK. A Write is performed by setting one or 5.
more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. Refer to the Write timing diagram for clarification.
Write Truth Table
Operation READ READ WRITE Byte 1 WRITE all bytes WRITE all bytes GW BWE BW1 BW2 BW3 BW4 H H X X X X H L H H H H H L L H H H H L L L L L L X X X X X PRELIMINARY (July, 2005, Version 0.0) 6
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A63L83361
Second Address (Internal)
X . . . X01 X . . . X10 X . . . X11 X . . . X00
Third Address (Internal)
X . . . X10 X . . . X11 X . . . X00 X . . . X01
Fourth Address (Internal)
X . . . X11 X . . . X00 X . . . X01 X . . . X10
Linear Burst Address Table (MODE = LOW)
First Address (External)
X . . . X00 X . . . X01 X . . . X10 X . . . X11
Interleaved Burst Address Table (MODE = HIGH or NC)
First Address (External)
X . . . X00 X . . . X01 X . . . X10 X . . . X11
Second Address (Internal)
X . . . X01 X . . . X00 X . . . X11 X . . . X10
Third Address (Internal)
X . . . X10 X . . . X11 X . . . X00 X . . . X01
VCC & VCCQ Supply Voltages
VCC for all devices . . ….. . . . . . . . . . . . . . . . . . . . +3.3V VCCQ for all devices . . ….. . . . . . . . . . . . . . . . . . . +3.3V Operating ranges define those limits between which the functionally of the device is guaranteed.
*Comments
Stresses above those listed under \"Absolute Maximum Ratings\" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
Fourth Address (Internal)
X . . . X11 X . . . X10 X . . . X01 X . . . X00
Absolute Maximum Ratings*
Power Supply Voltage (VCC) . . . . . . . . . . -0.5V to +4.6V Voltage Relative to GND for any Pin Except VCC (Vin, Vout) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . 2W Storage Temperature (Tbias) . . . . . . . . . . -65°C to 150 °C Storage Temperature (Tstg) . . . . . . . . . . . -55°C to 125°C
Operating Ranges Ambient Temperature
Commercial (C) Devices . . . . . . . . . . . . . . . 0°C to +70°C Industrial (I) Devices . . . . . . . . . . . . . . . -45°C to +125°C
Recommended DC Operating Conditions
(0°C ≤ TA ≤ 70°C, VCC, VCCQ = 3.3V+5% or 3.3V-5%, unless otherwise noted)
Symbol Parameter Min. Typ. Max. Unit Note VCC VCCQ GND VIH VIHQ VIL
Supply Voltage (Operating Voltage Range)
Isolated Input Buffer Supply Supply Voltage to GND Input High Voltage Input High Voltage (I/O Pins)
Input Low Voltage
3.135 3.135 0.0 2 2 -0.3
3.3 3.3 - - - -
3.465 3.465 0.0 VCC+0.3 VCC+0.3 0.8
V V V V V V
1, 2 1, 2
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A63L83361
DC Electrical Characteristics
(0°C ≤ TA ≤ 70°C, VCC, VCCQ = 3.3V+5% or 3.3V-5%, unless otherwise noted) Symbol Parameter Min. Max. Unit ⏐ILI⏐ ⏐ILO⏐ Test Conditions Note 3, 11 Input Leakage Current Output Leakage Current Supply Current - - - ±2.0 ±2.0 µA µA All inputs VIN = GND to VCC OE = VIH, Vout = GND to VCC Device selected; VCC = max. Iout = 0mA, all inputs = VIH or VIL Cycle time = tKC min. Device deselected; VCC = max. All inputs are fixed. All inputs ≥ VCC - 0.2V or ≤ GND + 0.2V Cycle time = tKC min. ICC1 300 mA ISB1 Standby Current - 30 mA 11 ISB2 VOL VOH Output Low Voltage Output High Voltage - - 1.6 15 mA ZZ ≥ VCC - 0.2V 1.0 - V V IOL = 8 mA IOH = -4 mA Capacitance
Symbol Parameter Typ. Max. Unit Conditions CIN Input Capacitance CI/O Input/Output Capacitance
* These parameters are sampled and not 100% tested.
3 4 pF TA = 25 C; f = 1MHz VCC = 3.3V
4 5 pF PRELIMINARY (July, 2005, Version 0.0) 8
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A63L83361
-6.5 -7.5 -8.5 UnitMax.- - - 6.5 - - 3.5 Min.8.5 2.8 2.8 - 3.0 2.5 - Max.- - - 7.5 - - 3.5 NoteAC Characteristics (0°C ≤ TA ≤ 70°C, VCC = 3.3V+5% or 3.3V-5%)
Symbol Parameter Min.TKC TKH TKL TKQ tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ Clock Cycle Time Clock High Time Clock Low Time Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock to Output in High-Z OE to Output Valid OE to Output in Low-Z OE to Output in High-Z 7.5 2.5 2.5 - 3.0 2.5 - Min. Max. 10 3.0 3.0 - 3.0 2.5 - - - - 8.5 - - 5.0 ns ns ns ns ns ns ns 5, 6 5, 6 - 3.5 - 3.5 - 5.0 ns 8 0 - 0 - 0 - ns 5, 6 - 3.5 - 3.5 - 5.0 ns 5, 6 Setup Times TAS Address tADSS tADVS tWS Address Status (ADSC, ADSP) Address Advance (ADV) Write Signals (BW1, BW2, BW3, BW4, BWE, GW) TDS Data-in tCES Chip Enable (CE, CE2, CE2) 1.5 - 1.5 - 2.0 - ns 7, 9 1.5 - 2.0 - 2.0 - ns 7, 9 1.5 - 2.0 - 2.0 - ns 7, 9 1.5 - 2.0 - 2.0 - ns 7, 9 1.5 - 2.0 - 2.0 - ns 7, 9 1.5 - 2.0 - 2.0 - ns 7, 9 Hold Times TAH Address tADSH tAAH tWH Address Status (ADSC, ADSP) Address Advance (ADV) Write Signal (BW1, BW2, BW3,BW4, BWE, GW) TDH Data-in tCEH Chip Enable (CE, CE2, CE2) 0.5 0.5 0.5 ns 7, 9 0.5 0.5 0.5 ns 7, 9 0.5 0.5 0.5 ns 7, 9 0.5 0.5 0.5 ns 7, 9 0.5 0.5 0.5 ns 7, 9 0.5 0.5 0.5 ns 7, 9 PRELIMINARY (July, 2005, Version 0.0) 9
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Notes:
A63L83361
1. All voltages refer to GND.
2. Overshoot: VIH ≤ +2V for t ≤ tKC/2. Undershoot: VIL ≥ -0.7V for t ≤ tKC/2. Power-up: VIH ≤ +2 and VCC ≤ 1.7V
≤ 200ms for t
3. ICC1 is given with no output current. ICC1 increases with greater output loading and faster cycle times. 4. Test conditions assume the output loading shown in Figure 1, unless otherwise specified.
5. For output loading, CL = 5pF, as shown in Figure 2. Transition is measured ±150mV from steady state voltage. 6. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tQELZ.
7. A WRITE cycle is defined by at least one Byte Write enable LOW and ADSP HIGH for the required setup and hold times. A READ cycle is defined by all byte write enables HIGH and (ADSC or ADV LOW) or ADSP LOW for the required setup and hold times.
8. OE has no effect when a Byte Write enable is sampled LOW.
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
ADSP or ADSC is LOW and the chip is enabled. All other synchronous inputs must meet the setup and when either
hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP or ADSC is LOW to remain enabled.
10. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the given DC values. AC I/O curves are available upon request.
11. \"Device Deselected\" means device is in POWER-DOWN mode, as defined in the truth table. \"Device Selected\" means device is active (not in POWER-DOWN mode).
12. MODE pin has an internal pulled-up, and ZZ pin has an internal pulled-down. All of then exhibit an input leakage current of 10µA.
13. Snooze (ZZ) input is recommended that users plan for four clock cycles to go into SLEEP mode and four clocks to emerge from SLEEP mode to ensure no data is lost.
PRELIMINARY (July, 2005, Version 0.0) 10
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A63L83361
Timing Waveforms
tKCCLKtKHtADSSADSPtADSSADSCtASADDRESSA1tWSGW,BWEBW1-BW4tCESCE(NOTE 2)tADVSADVADV suspends burstOE(NOTE 3)tOEQtKQLZDOUTHigh-ZtKQSingle READQ(A1)tOELZtOEHZtKQXQ(A2)Q(A2+1)(NOTE *1)BURST READQ(A2+2)Q(A2+3)tKQtKQXQ(A3)tKQHZtADVHtCEHDeselect with CEtWHtAHA2A3tADSHDeselect cycletADSHtKLDon't CareUndefined
Read Timing
Notes: 1. QA(2) refers to output from address A2. Q(A2+1) refers to output from the next internal burst address following A2.
CE and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. 2.
WhenCE is HIGH, CE2 is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE does not cause Q to be driven until after the following clock rising edge.
PRELIMINARY (July, 2005, Version 0.0) 11
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A63L83361
tKCTiming Waveforms (continued)
CLKtKHtADSSADSPtADSSADSCtASADDRESSA1tAHA2BYTE WRITE signals are ignoredfor first cycle when ADSP initiates burstBWE,BW1-BW4(NOTE 5)tWSGWtCESCE(NOTE 2)tADVSADV(NOTE 4)OEADV suspends bursttADVHtCEHtWHA3tWStWHtADSHADSC extends bursttADSStADSHtADSHtKL(NOTE 3)tDStDHD(A1)tOEHZD(A2)D(A2+1)(NOTE 1)D(A2+1)D(A2+2)D(A2+3)D(A3)D(A3+1)D(A3+2)DINHigh-ZDOUTBURST READSingle WRITEExtended BURST WRITEDon't CareUndefined
Write Timing
Notes: 1. D(A2) refers to output from address A2. D(A2+1) refers to output from the internal burst address immediately following A2.
CE2 and CE2 is identical to that for CE. As shown in the above diagram, when CE is LOW, CE2 2. Timing for
is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
OE must be HIGH before the input data setup, and held HIGH throughout the data hold period. This prevents 3.
input/output data contention for the period prior to the time Byte Write enable inputs are sampled.
ADV must be HIGH to permit a Write to the loaded address. 4.
5. Byte Write enables are decided by means of a Write truth table.
PRELIMINARY (July, 2005, Version 0.0) 12
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A63L83361
tKCTiming Waveforms (continued)
CLKtKHtADSSADSPtADSHtKLADSCtAStAHADDRESSA1A2A3tWSGW,BWE,BW1-BW4(NOTE 3)tCESCE(NOTE 2)tCEHtWHA4A5A6ADVOEtKQDINHigh-ZtOEHZtKQDOUTQ(A1)Q(A2)Single WRITEQ(A4)(NOTE 1)Q(A4+1)Q(A4+2)Q(A4+3)Back-to-BackWRITEstDStDHD(A3)tOELZD(A5)D(A6)Back-to-Back READsBURST READDon't CareUndefined
Read/Write Timing
Notes: 1. Q(A4) refers to output from address A4. Q(A4+1) refers to output from the next internal burst address following A4.
CE2 and CE2 have timing identical to CE. On this diagram, whenCE is LOW, CE is LOW and CE2 is HIGH, 2.
When CE is HIGH, CE2 is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP,ADSC, or ADVcycle is
performed.
4. Byte Write enables are decided by means of a Write truth table.
5. Back-to-back READs may be controlled by either ADSPor ADSC
PRELIMINARY (July, 2005, Version 0.0) 13
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A63L83361
GND to 3V 1 ns 1.5V VccQ/2 See Figures 1 and 2
AC Test Conditions
Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Reference Levels Output Load
Figure 1. Output Load Equivalent Figure
Q
ZO=50ΩRL=50Ω
VT=0.75V2. Output Load Equivalent
VCCQ/250ΩQ
5pF
Ordering Information
Part No.
Access Times (ns)
Frequency (MHz)
Package
A63L83361E-6.5 6.5 A63L83361E-6.5F
6.5
153 100L LQFP 153
100L Pb-Free LQFP
A63L83361E-7.5 7.5 A63L83361E-7.5F
7.5
133 100L LQFP 133
100L Pb-Free LQFP
A63L83361E-8 8 117 100L LQFP A63L83361E-8F
8
117
100L Pb-Free LQFP
PRELIMINARY (July, 2005, Version 0.0) 14
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A63L83361
unit: inches/mm
Package Information
LQFP 100L Outline Dimensions
HEE8051A2A1yD8150HDD10031130ebcθ Symbol Dimensions in inchesNom.0.0550.0130.8660.7870.6300.5510.026 BSC 0.0240.039 REF 0.030Max.0.0570.0150.8720.7910.6360.555Dimensions in mm Min. Nom.Max. Min.A1 0.002A2 0.053b 0.011c 0.005HE 0.860E 0.783HD 0.624D 0.547e L 0.018L1 - - 0.05 - - 1.35 1.40 1.450.27 0.32 0.370.12 - 0.2023.3519.9015.8513.9022.0020.0016.0014.000.65 BSC 0.45 0.60 0.751.00 REF - - 0.1 0° 3.5° 7° 22.1520.1016.1514.10- 0.008y - - 0.004θ 0° 3.5° 7° Notes:
1. Dimensions D and E do not include mold protrusion. 2. Dimensions b does not include dambar protrusion.
Total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot.
LL1PRELIMINARY (July, 2005, Version 0.0) 15
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